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    <title>topic LX2160ARDB platform clk in Layerscape</title>
    <link>https://community.nxp.com/t5/Layerscape/LX2160ARDB-platform-clk/m-p/1401465#M9871</link>
    <description>&lt;P&gt;We are developing a UART driver for LX2160ARDB_rev2.&lt;/P&gt;&lt;P&gt;I am using "platform clk" to calculate the baud rate, but I don't know how to get it on SW.&lt;BR /&gt;It is known from the U-boot source code that the platform clk is a bus clock, and it is known from RCW and U-boot that the bus clock is 750 MHz.&lt;/P&gt;&lt;P&gt;Based on this value, you can pre-calculate and hold it as a constant, but it is smarter to get it from a register and calculate it.&lt;/P&gt;&lt;P&gt;However, there is no mention of platform clk in the "QorIQ LX2160A Reference Manual Supports LX2120A and LX2080A", so I don't know where I can get it from.&lt;/P&gt;&lt;P&gt;Is it easy to get a platform clk, or even a bus clock?&lt;/P&gt;</description>
    <pubDate>Wed, 19 Jan 2022 07:23:11 GMT</pubDate>
    <dc:creator>m_kei</dc:creator>
    <dc:date>2022-01-19T07:23:11Z</dc:date>
    <item>
      <title>LX2160ARDB platform clk</title>
      <link>https://community.nxp.com/t5/Layerscape/LX2160ARDB-platform-clk/m-p/1401465#M9871</link>
      <description>&lt;P&gt;We are developing a UART driver for LX2160ARDB_rev2.&lt;/P&gt;&lt;P&gt;I am using "platform clk" to calculate the baud rate, but I don't know how to get it on SW.&lt;BR /&gt;It is known from the U-boot source code that the platform clk is a bus clock, and it is known from RCW and U-boot that the bus clock is 750 MHz.&lt;/P&gt;&lt;P&gt;Based on this value, you can pre-calculate and hold it as a constant, but it is smarter to get it from a register and calculate it.&lt;/P&gt;&lt;P&gt;However, there is no mention of platform clk in the "QorIQ LX2160A Reference Manual Supports LX2120A and LX2080A", so I don't know where I can get it from.&lt;/P&gt;&lt;P&gt;Is it easy to get a platform clk, or even a bus clock?&lt;/P&gt;</description>
      <pubDate>Wed, 19 Jan 2022 07:23:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LX2160ARDB-platform-clk/m-p/1401465#M9871</guid>
      <dc:creator>m_kei</dc:creator>
      <dc:date>2022-01-19T07:23:11Z</dc:date>
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    <item>
      <title>Re: LX2160ARDB platform clk</title>
      <link>https://community.nxp.com/t5/Layerscape/LX2160ARDB-platform-clk/m-p/1401543#M9872</link>
      <description>&lt;P&gt;Refer to the QorIQ LX2160A Reference Manual, 4.10 IP Logic Clock Distribution and Configuration to see:&lt;/P&gt;&lt;P&gt;1) &lt;STRONG&gt;Platform PLL&lt;/STRONG&gt; is controlled by&amp;nbsp;RCW[&lt;STRONG&gt;SYS_PLL_RAT&lt;/STRONG&gt;]&lt;/P&gt;&lt;P&gt;2) &lt;STRONG&gt;Platform clock&lt;/STRONG&gt; is &lt;STRONG&gt;Platform PLL / 2&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;3) UART is clocked by &lt;STRONG&gt;Platform clock / 4&lt;/STRONG&gt;.&lt;/P&gt;&lt;P&gt;Refer to the RM, 9.3.1.13 Reset Configuration Word Status Register 1 (RCWSR1) to obtain the &lt;STRONG&gt;SYS_PLL_RAT&lt;/STRONG&gt; value.&lt;/P&gt;</description>
      <pubDate>Wed, 19 Jan 2022 08:35:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LX2160ARDB-platform-clk/m-p/1401543#M9872</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2022-01-19T08:35:19Z</dc:date>
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