https://community.nxp.com/t5/Layerscape/16-bit-QSPI-chip-with-LS1046A-based-board/m-p/1395754#M9790 <P>Hi,</P><P>We have a 16-bit QSPI chip we are trying to use as the boot device for our LS1046A-based board.&nbsp; We noticed in the LS1046A FRWY initialization PBI commands there is a command that looks like it's setting the QuadSPI_MCR to 64-bit LE (write 0x550000, 0x000f400c).</P><P>Questions:</P><P>Are we able to use 16-bit QuadSPI on with the LS1046A? It looks like all the NXP designs use 8-bit QSPI, which is probably compatible with switching the endianness like this.</P><P>Will a 16-bit QSPI be able to endian swap on the qspi controller?</P> Thu, 06 Jan 2022 19:21:42 GMT JRRandall 2022-01-06T19:21:42Z https://community.nxp.com/t5/Layerscape/16-bit-QSPI-chip-with-LS1046A-based-board/m-p/1395754#M9790 <P>Hi,</P><P>We have a 16-bit QSPI chip we are trying to use as the boot device for our LS1046A-based board.&nbsp; We noticed in the LS1046A FRWY initialization PBI commands there is a command that looks like it's setting the QuadSPI_MCR to 64-bit LE (write 0x550000, 0x000f400c).</P><P>Questions:</P><P>Are we able to use 16-bit QuadSPI on with the LS1046A? It looks like all the NXP designs use 8-bit QSPI, which is probably compatible with switching the endianness like this.</P><P>Will a 16-bit QSPI be able to endian swap on the qspi controller?</P> Thu, 06 Jan 2022 19:21:42 GMT https://community.nxp.com/t5/Layerscape/16-bit-QSPI-chip-with-LS1046A-based-board/m-p/1395754#M9790 JRRandall 2022-01-06T19:21:42Z https://community.nxp.com/t5/Layerscape/16-bit-QSPI-chip-with-LS1046A-based-board/m-p/1395923#M9791 <P>QSPI controller endianness is configured for internal data exchange and is independent of the connected SPI device.</P> Fri, 07 Jan 2022 05:14:02 GMT https://community.nxp.com/t5/Layerscape/16-bit-QSPI-chip-with-LS1046A-based-board/m-p/1395923#M9791 ufedor 2022-01-07T05:14:02Z