LayerscapeのトピックRe: LS1012A Serdes options

LS1012A Serdes options

victor0123 — Thu, 30 Dec 2021 05:30:24 GMT

In my PCB,LS1012A Serdes lane A:SGMII1,lane B:SGMII2,lane D:PCIE(Endpoint).

SRDS_PRTCL_S1 RCW[128:143]=3305.

SD1_REF_CLK1_P/N PIN is provided 100Mhz from X86 DEMO.

The PCIE of X86 DEMO is configured to operate as a PCI Express Root Complex.

LS1012A is configured to operate as a Endpoint device.

But <QorIQ LS1012A Reference Manual >Page 234

Setting this bit to 0 is only supported with
SerDes protocol option (SRDS_PRTCL_S1) =
0x0005 ?

SGMII1 and SGMII2 can not work?

Re: LS1012A Serdes options

ufedor — Thu, 30 Dec 2021 05:52:17 GMT

Proper operation of SGMII1 and SGMII2 cannot be guaranteed when LS1012A SerDes reference clock is provided by a PCIe RC because spread-spectrum can be used.

Re: LS1012A Serdes options

victor0123 — Thu, 30 Dec 2021 07:36:40 GMT

Thanks for your reply.

If the 100Mhz reference clock provided by a PCIe RC is not a spread-spectrum，SGMII can work,right?

Re: LS1012A Serdes options

ufedor — Thu, 30 Dec 2021 08:01:03 GMT

Technically SGMII should work in the described case, but configuration in question was not validated during LS1012A silicon bring-up.