https://community.nxp.com/t5/Layerscape/LS1043A-GIC-and-SMMU/m-p/1392949#M9745 <P>What is version of GIC in LS1043A?</P><P>Does SMMU of LS1043A support stage 2 io translation?</P> Wed, 29 Dec 2021 08:11:07 GMT jjmac 2021-12-29T08:11:07Z https://community.nxp.com/t5/Layerscape/LS1043A-GIC-and-SMMU/m-p/1392949#M9745 <P>What is version of GIC in LS1043A?</P><P>Does SMMU of LS1043A support stage 2 io translation?</P> Wed, 29 Dec 2021 08:11:07 GMT https://community.nxp.com/t5/Layerscape/LS1043A-GIC-and-SMMU/m-p/1392949#M9745 jjmac 2021-12-29T08:11:07Z https://community.nxp.com/t5/Layerscape/LS1043A-GIC-and-SMMU/m-p/1393007#M9747 <P>1) Please refer to the QorIQ LS1043A Reference Manual, Table 6-1. Related resources from Arm:</P> <P> <span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="LS1043A_ARM_IP.jpg" style="width: 667px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/166442i898BCC2CA4C6285D/image-dimensions/667x120?v=v2" width="667" height="120" role="button" title="LS1043A_ARM_IP.jpg" alt="LS1043A_ARM_IP.jpg" /><span class="lia-inline-image-caption" onclick="event.preventDefault();">LS1043A_ARM_IP.jpg</span></span></P> <P>2) The MMU-500 supports the stage 2 translations that translate an input IPA to an output PA.</P> <P>Refer to the ARM® CoreLink™ MMU-500 System Memory Management Unit<BR />Technical Reference Manual</P> <P>1.1 About the MMU-500</P> Wed, 29 Dec 2021 09:55:39 GMT https://community.nxp.com/t5/Layerscape/LS1043A-GIC-and-SMMU/m-p/1393007#M9747 ufedor 2021-12-29T09:55:39Z