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    <title>Layerscape中的主题 mocrochip ksz8795 switch on LS1012a</title>
    <link>https://community.nxp.com/t5/Layerscape/mocrochip-ksz8795-switch-on-LS1012a/m-p/1390956#M9688</link>
    <description>&lt;P&gt;We have a custom board using a Layerscape ls1012a processor hooked up in the following manner.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="WAPII_EnetConnections.gif" style="width: 504px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/166007iF8C5C945144281C6/image-size/large?v=v2&amp;amp;px=999" role="button" title="WAPII_EnetConnections.gif" alt="WAPII_EnetConnections.gif" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;We are building openwrt with a 5.4 kernel that has divers for both chips. However, we are struggling to get our device tree configured so that either chip is probed correctly. We believe our RCW is configured correctly but we get a MDIO "device at address 0 is missing" when probing the MDIO bus and we get an error -22 (bad parameter) for the SPI switch.&lt;/P&gt;&lt;P&gt;We have tracked the SPI switch error to it not finding the phy-mode node even though we have it in several places.&lt;/P&gt;&lt;P&gt;Below are the relevent parts of our device tree.&lt;/P&gt;&lt;LI-CODE lang="markup"&gt;&amp;amp;pfe {
      	status = "okay";
        #address-cells = &amp;lt;1&amp;gt;;
        #size-cells = &amp;lt;0&amp;gt;;

        pfe_mac0: ethernet@0 {
                compatible = "fsl,pfe-gemac-port";
                #address-cells = &amp;lt;1&amp;gt;;
                #size-cells = &amp;lt;0&amp;gt;;
                reg = &amp;lt;0x0&amp;gt;;    /* GEM_ID */
                fsl,mdio-mux-val = &amp;lt;0x0&amp;gt;;
                phy-mode = "sgmii";
                phy-handle = &amp;lt;&amp;amp;wan_phy&amp;gt;;
        };

	pfe_mac1: ethernet@1 {
                phy-mode = "rgmii";
                #address-cells = &amp;lt;1&amp;gt;;
                #size-cells = &amp;lt;0&amp;gt;;
                reg = &amp;lt;0x1&amp;gt;;
                fixed-link {
                        speed = &amp;lt;1000&amp;gt;;
                        full-duplex;
                };
        };
	mdio@0 {
                #address-cells = &amp;lt;1&amp;gt;;
                #size-cells = &amp;lt;0&amp;gt;;

                wan_phy: ethernet-phy@0 {
                        reg = &amp;lt;0x0&amp;gt;; /* Phy Address on mdio bus */
                        //phy-mode = "sgmii";
                        tx-fifo-depth = &amp;lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&amp;gt;;
                };
        };
};&lt;/LI-CODE&gt;&lt;LI-CODE lang="markup"&gt;&amp;amp;dspi {
       	status = "okay";

        ksz8794: ksz8794@0 {
                status = "okay";
                compatible = "microchip,ksz8794";
                reg = &amp;lt;0&amp;gt;;

                spi-max-frequency = &amp;lt;10000000&amp;gt;;
                spi-cpha;
                spi-cpol;

                ports {
                        #address-cells = &amp;lt;1&amp;gt;;
                        #size-cells = &amp;lt;0&amp;gt;;
                        port@0 {
                                reg = &amp;lt;0&amp;gt;;
                                label = "lan1";
                        };
                        port@1 {
                                reg = &amp;lt;1&amp;gt;;
                                label = "lan2";
                        };
                        port@2 {
                                reg = &amp;lt;2&amp;gt;;
                                label = "lan3";
                        };
                        port@3 {
                                reg = &amp;lt;4&amp;gt;;
                                label = "cpu";
                                ethernet = &amp;lt;&amp;amp;pfe_mac1&amp;gt;;
                                phy-mode = "rgmii";
                                fixed-link {
                                        speed = &amp;lt;1000&amp;gt;;
                                        full-duplex;
                                };
                        };
                };
        };
};&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Any help or direction would be appreciated.&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Thu, 23 Dec 2021 00:06:12 GMT</pubDate>
    <dc:creator>reginaldstjohn</dc:creator>
    <dc:date>2021-12-23T00:06:12Z</dc:date>
    <item>
      <title>mocrochip ksz8795 switch on LS1012a</title>
      <link>https://community.nxp.com/t5/Layerscape/mocrochip-ksz8795-switch-on-LS1012a/m-p/1390956#M9688</link>
      <description>&lt;P&gt;We have a custom board using a Layerscape ls1012a processor hooked up in the following manner.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="WAPII_EnetConnections.gif" style="width: 504px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/166007iF8C5C945144281C6/image-size/large?v=v2&amp;amp;px=999" role="button" title="WAPII_EnetConnections.gif" alt="WAPII_EnetConnections.gif" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;We are building openwrt with a 5.4 kernel that has divers for both chips. However, we are struggling to get our device tree configured so that either chip is probed correctly. We believe our RCW is configured correctly but we get a MDIO "device at address 0 is missing" when probing the MDIO bus and we get an error -22 (bad parameter) for the SPI switch.&lt;/P&gt;&lt;P&gt;We have tracked the SPI switch error to it not finding the phy-mode node even though we have it in several places.&lt;/P&gt;&lt;P&gt;Below are the relevent parts of our device tree.&lt;/P&gt;&lt;LI-CODE lang="markup"&gt;&amp;amp;pfe {
      	status = "okay";
        #address-cells = &amp;lt;1&amp;gt;;
        #size-cells = &amp;lt;0&amp;gt;;

        pfe_mac0: ethernet@0 {
                compatible = "fsl,pfe-gemac-port";
                #address-cells = &amp;lt;1&amp;gt;;
                #size-cells = &amp;lt;0&amp;gt;;
                reg = &amp;lt;0x0&amp;gt;;    /* GEM_ID */
                fsl,mdio-mux-val = &amp;lt;0x0&amp;gt;;
                phy-mode = "sgmii";
                phy-handle = &amp;lt;&amp;amp;wan_phy&amp;gt;;
        };

	pfe_mac1: ethernet@1 {
                phy-mode = "rgmii";
                #address-cells = &amp;lt;1&amp;gt;;
                #size-cells = &amp;lt;0&amp;gt;;
                reg = &amp;lt;0x1&amp;gt;;
                fixed-link {
                        speed = &amp;lt;1000&amp;gt;;
                        full-duplex;
                };
        };
	mdio@0 {
                #address-cells = &amp;lt;1&amp;gt;;
                #size-cells = &amp;lt;0&amp;gt;;

                wan_phy: ethernet-phy@0 {
                        reg = &amp;lt;0x0&amp;gt;; /* Phy Address on mdio bus */
                        //phy-mode = "sgmii";
                        tx-fifo-depth = &amp;lt;DP83867_PHYCR_FIFO_DEPTH_4_B_NIB&amp;gt;;
                };
        };
};&lt;/LI-CODE&gt;&lt;LI-CODE lang="markup"&gt;&amp;amp;dspi {
       	status = "okay";

        ksz8794: ksz8794@0 {
                status = "okay";
                compatible = "microchip,ksz8794";
                reg = &amp;lt;0&amp;gt;;

                spi-max-frequency = &amp;lt;10000000&amp;gt;;
                spi-cpha;
                spi-cpol;

                ports {
                        #address-cells = &amp;lt;1&amp;gt;;
                        #size-cells = &amp;lt;0&amp;gt;;
                        port@0 {
                                reg = &amp;lt;0&amp;gt;;
                                label = "lan1";
                        };
                        port@1 {
                                reg = &amp;lt;1&amp;gt;;
                                label = "lan2";
                        };
                        port@2 {
                                reg = &amp;lt;2&amp;gt;;
                                label = "lan3";
                        };
                        port@3 {
                                reg = &amp;lt;4&amp;gt;;
                                label = "cpu";
                                ethernet = &amp;lt;&amp;amp;pfe_mac1&amp;gt;;
                                phy-mode = "rgmii";
                                fixed-link {
                                        speed = &amp;lt;1000&amp;gt;;
                                        full-duplex;
                                };
                        };
                };
        };
};&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Any help or direction would be appreciated.&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 23 Dec 2021 00:06:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/mocrochip-ksz8795-switch-on-LS1012a/m-p/1390956#M9688</guid>
      <dc:creator>reginaldstjohn</dc:creator>
      <dc:date>2021-12-23T00:06:12Z</dc:date>
    </item>
    <item>
      <title>Re: mocrochip ksz8795 switch on LS1012a</title>
      <link>https://community.nxp.com/t5/Layerscape/mocrochip-ksz8795-switch-on-LS1012a/m-p/1395438#M9787</link>
      <description>&lt;P&gt;I do not see anything wrong in the DT declaration of the PHY connected directly&lt;BR /&gt;to SGMII/pfe_mac0. The diagnostic message you are seeing tells that the kernel&lt;BR /&gt;actually attempts to find the PHY where the DT instructs it to. The error &lt;BR /&gt;appears most likely because the driver does not get the expected response from&lt;BR /&gt;the PHY.&lt;/P&gt;
&lt;P&gt;As of the switch and it's driver, it is not an NXP product. We do not have &lt;BR /&gt;expertise in this device and cannot advice on configuring and using it, sorry.&lt;BR /&gt;Our suggestion in this regard is to approach the switch vendor for support.&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;BR /&gt;Platon&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 06 Jan 2022 07:48:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/mocrochip-ksz8795-switch-on-LS1012a/m-p/1395438#M9787</guid>
      <dc:creator>bpe</dc:creator>
      <dc:date>2022-01-06T07:48:17Z</dc:date>
    </item>
    <item>
      <title>Re: mocrochip ksz8795 switch on LS1012a</title>
      <link>https://community.nxp.com/t5/Layerscape/mocrochip-ksz8795-switch-on-LS1012a/m-p/1395725#M9789</link>
      <description>&lt;P&gt;We have found that the problem is that the driver is written to not expect more then 3 ports even though the documentation clearly states that we should have our device tree as above. It seems that in our codebase, Openwrt, the driver is not written correctly.&amp;nbsp; It seems, to us, that the driver was never tested or was written for a different device tree.&lt;/P&gt;&lt;P&gt;In the mainline Linux Kernel there are patches trying to fix issues similar to ours. We will have to look at backporting a driver to our kernel version, 5.10 I believe, or upgrading our distribution to see if the fixes have been applied.&lt;/P&gt;</description>
      <pubDate>Thu, 06 Jan 2022 16:48:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/mocrochip-ksz8795-switch-on-LS1012a/m-p/1395725#M9789</guid>
      <dc:creator>reginaldstjohn</dc:creator>
      <dc:date>2022-01-06T16:48:12Z</dc:date>
    </item>
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