https://community.nxp.com/t5/Layerscape/LS1043a-Interrupt-Priority/m-p/1390796#M9687 <P>Hello everyone,<BR />I found out thanks to the document <STRONG>QorIQ LS1043A Reference Manual, Rev. 6, 07/2020, </STRONG><SPAN class=""><SPAN class=""><SPAN>that the ls1043a processor has the following list of external interrupt input signals</SPAN></SPAN></SPAN>:</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Capture.PNG" style="width: 694px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/165979iB10895D81D5A34E3/image-size/large?v=v2&amp;px=999" role="button" title="Capture.PNG" alt="Capture.PNG" /></span></P><P>These interrupt input signals are connected to the Arm generic interrupt controller (GIC-400).</P><P>I wanted to know<STRONG> if there was a concept of priority over interrupts among these interrupt input signals</STRONG>.<BR />If priority is present, <STRONG>is the priority of these interrupts programmable?</STRONG></P> Wed, 22 Dec 2021 13:16:59 GMT notshure 2021-12-22T13:16:59Z https://community.nxp.com/t5/Layerscape/LS1043a-Interrupt-Priority/m-p/1390796#M9687 <P>Hello everyone,<BR />I found out thanks to the document <STRONG>QorIQ LS1043A Reference Manual, Rev. 6, 07/2020, </STRONG><SPAN class=""><SPAN class=""><SPAN>that the ls1043a processor has the following list of external interrupt input signals</SPAN></SPAN></SPAN>:</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Capture.PNG" style="width: 694px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/165979iB10895D81D5A34E3/image-size/large?v=v2&amp;px=999" role="button" title="Capture.PNG" alt="Capture.PNG" /></span></P><P>These interrupt input signals are connected to the Arm generic interrupt controller (GIC-400).</P><P>I wanted to know<STRONG> if there was a concept of priority over interrupts among these interrupt input signals</STRONG>.<BR />If priority is present, <STRONG>is the priority of these interrupts programmable?</STRONG></P> Wed, 22 Dec 2021 13:16:59 GMT https://community.nxp.com/t5/Layerscape/LS1043a-Interrupt-Priority/m-p/1390796#M9687 notshure 2021-12-22T13:16:59Z https://community.nxp.com/t5/Layerscape/LS1043a-Interrupt-Priority/m-p/1395593#M9788 <P><SPAN>The priority of these interrupts can be set using Interrupt Priority Registers. Refer Table 3-2 Distributor register summary&nbsp; in GIC-400 Technical Reference Manual (&nbsp;</SPAN><A id="LPlnk624860" href="https://developer.arm.com/documentation/ddi0471/b)" target="_blank" rel="noopener noreferrer" data-auth="NotApplicable" data-linkindex="0">https://developer.arm.com/documentation/ddi0471/b)</A><SPAN>. Also refer ARM Generic Interrupt Controller Architecture Specification for Priority registers.</SPAN></P> Thu, 06 Jan 2022 11:46:00 GMT https://community.nxp.com/t5/Layerscape/LS1043a-Interrupt-Priority/m-p/1395593#M9788 andrei_skok 2022-01-06T11:46:00Z