DDR BIT (Build In Test)

notshure — Wed, 01 Dec 2021 09:59:39 GMT

Hi all I'm working with the LS1043a processor.
I wanted to know if this processor inside the DDR memory controller has a self test of the DDR memories a BIT test integrated into the hardware.

Is there a field of a register of the DDR Controller in which setting it to "1", is it possible to perform a Hardware test on the DDR?

Having the ability to perform a hardware-level test of this type, speeds up my boot process.
Otherwise I would have to test the DDR memory via software by writing and reading to each memory location in the DDR.
Considering that the memory is 2Gb the test done via Software becomes quite slow.

Thanks

Re: DDR BIT (Build In Test)

ufedor — Wed, 01 Dec 2021 12:59:31 GMT

The test is explained under the register setting DDR_MTCR. These memory tests have 40-byte data test patterns repeated and used for the test. The data patterns are populated at the 10 DDR_MTP registers. The test can be read only, write only, or write-read-compare selectable with DDR_MTCR[MT_TYP]. If a range is enabled via DDR_MTCR[MT_ADDR_EN], then a range of starting and ending address should be programed via DDR_MT_ST_ADDR and DDR_MT_END_ADDR registers. If range is not enabled the test will be conducted through entire memory defined by the CSn_BNDS registers.
There is also a selection on how the write-read-compare test should be done, whether 1 write burst, then 1 read burst and then compare. Or 2W, 2R. or ..., or write the entire range, then read the entire range. This selection is done via setting at DDR_MTCR[MT_TRANRND].
To start the test set the DDR_MTCR[MT_EN]. If the test completes, then the DDR_MTCR[MT_EN] will be cleared by HW. If test completes and there are test fails because of a comparison failure then a failure flag is set in DDR_MTCR[MT_STAT]. A test is considered passed when MT_EN clears and MT_STAT = 0.

Please refer to the QorIQ LS1043A Reference Manual:

18.4.59 DDR Memory Test Control Register (DDR_MTCR)

18.4.60 DDR Memory Test Pattern n Register (DDR_MTP0 - DDR_MTP9)

18.4.61 DDR Memory Test Start Extended Address (DDR_MT_ST_EXT_ADDR)

18.4.62 DDR Memory Test Start Address (DDR_MT_ST_ADDR)

18.4.63 DDR Memory Test End Extended Address (DDR_MT_END_EXT_ADDR)

18.4.64 DDR Memory Test End Address (DDR_MT_END_ADDR)

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DDR BIT (Build In Test)

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