<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
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    <title>LayerscapeのトピックBare board based on LS1046ardb booting from NOR problem</title>
    <link>https://community.nxp.com/t5/Layerscape/Bare-board-based-on-LS1046ardb-booting-from-NOR-problem/m-p/1377209#M9502</link>
    <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;we have designed a small processor module, based on LS1046ardb,&lt;/P&gt;&lt;P&gt;with an additional parallel NOR flash&amp;nbsp; and SD card&lt;/P&gt;&lt;P&gt;We can boot a uboot from SD card, built with LS1046ardb_sdcard_defconfig without any problems.&lt;/P&gt;&lt;P&gt;at bootloader CLI we can erase/program the NOR flash,&amp;nbsp;&lt;/P&gt;&lt;P&gt;flinfo shows correct type of component, that means hardware is ok.&lt;/P&gt;&lt;P&gt;Now we want to boot from NOR, we commented out "CONFIG_SD_BOOT=y"&lt;/P&gt;&lt;P&gt;and changed&amp;nbsp; &amp;nbsp;"CONFIG_SYS_TEXT_BASE=0x60100000",&amp;nbsp;&lt;/P&gt;&lt;P&gt;because NOR is configured to IFC 0x60000000&lt;/P&gt;&lt;P&gt;1. question,&lt;/P&gt;&lt;P&gt;after compiling the scripts doesn't generates&lt;/P&gt;&lt;P&gt;u-boot-with-spl.bin and u-boot-with-spl-pbl.bin, which contains rcw+pbl+uboot.&lt;/P&gt;&lt;P&gt;it generates only u-boot.bin, u-boot-dtb.bin, u-boot-nodtb.bin&lt;/P&gt;&lt;P&gt;2. we used a rcw in processor.pe project, based on the rcw for sd card boot and changed PBI_SRC to IFC only, and programmed rcw to 0x60000000 and&lt;/P&gt;&lt;P&gt;u-boot.bin to 0x60100000,&lt;/P&gt;&lt;P&gt;no success&lt;/P&gt;&lt;P&gt;3. do we have to add the additional PBI data, stored in ls1046ardb_pbi.cfg ?&lt;/P&gt;&lt;P&gt;4. Where we have to configure the PBL to find the bootloader entry at 0x60100000 ?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks for any hints,&lt;/P&gt;&lt;P&gt;Mike&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Thu, 25 Nov 2021 17:54:46 GMT</pubDate>
    <dc:creator>micha</dc:creator>
    <dc:date>2021-11-25T17:54:46Z</dc:date>
    <item>
      <title>Bare board based on LS1046ardb booting from NOR problem</title>
      <link>https://community.nxp.com/t5/Layerscape/Bare-board-based-on-LS1046ardb-booting-from-NOR-problem/m-p/1377209#M9502</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;we have designed a small processor module, based on LS1046ardb,&lt;/P&gt;&lt;P&gt;with an additional parallel NOR flash&amp;nbsp; and SD card&lt;/P&gt;&lt;P&gt;We can boot a uboot from SD card, built with LS1046ardb_sdcard_defconfig without any problems.&lt;/P&gt;&lt;P&gt;at bootloader CLI we can erase/program the NOR flash,&amp;nbsp;&lt;/P&gt;&lt;P&gt;flinfo shows correct type of component, that means hardware is ok.&lt;/P&gt;&lt;P&gt;Now we want to boot from NOR, we commented out "CONFIG_SD_BOOT=y"&lt;/P&gt;&lt;P&gt;and changed&amp;nbsp; &amp;nbsp;"CONFIG_SYS_TEXT_BASE=0x60100000",&amp;nbsp;&lt;/P&gt;&lt;P&gt;because NOR is configured to IFC 0x60000000&lt;/P&gt;&lt;P&gt;1. question,&lt;/P&gt;&lt;P&gt;after compiling the scripts doesn't generates&lt;/P&gt;&lt;P&gt;u-boot-with-spl.bin and u-boot-with-spl-pbl.bin, which contains rcw+pbl+uboot.&lt;/P&gt;&lt;P&gt;it generates only u-boot.bin, u-boot-dtb.bin, u-boot-nodtb.bin&lt;/P&gt;&lt;P&gt;2. we used a rcw in processor.pe project, based on the rcw for sd card boot and changed PBI_SRC to IFC only, and programmed rcw to 0x60000000 and&lt;/P&gt;&lt;P&gt;u-boot.bin to 0x60100000,&lt;/P&gt;&lt;P&gt;no success&lt;/P&gt;&lt;P&gt;3. do we have to add the additional PBI data, stored in ls1046ardb_pbi.cfg ?&lt;/P&gt;&lt;P&gt;4. Where we have to configure the PBL to find the bootloader entry at 0x60100000 ?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks for any hints,&lt;/P&gt;&lt;P&gt;Mike&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 25 Nov 2021 17:54:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Bare-board-based-on-LS1046ardb-booting-from-NOR-problem/m-p/1377209#M9502</guid>
      <dc:creator>micha</dc:creator>
      <dc:date>2021-11-25T17:54:46Z</dc:date>
    </item>
    <item>
      <title>Re: Bare board based on LS1046ardb booting from NOR problem</title>
      <link>https://community.nxp.com/t5/Layerscape/Bare-board-based-on-LS1046ardb-booting-from-NOR-problem/m-p/1377493#M9506</link>
      <description>&lt;P&gt;LS1046AQDS integrates IFC NOR flash boot, you could customize your source code referring to ls1046aqds.&lt;/P&gt;
&lt;P&gt;Please refer to include/configs/ls1046aqds.h and configs/ls1046aqds_defconfig in u-boot source code.&lt;/P&gt;
&lt;P&gt;1. When comping IFC NOR flash u-boot, only u-boot image is generated, which doesn't include RCW+PBI. You need to program PBL(RCW+PBI) image separately.&lt;/P&gt;
&lt;P&gt;2. I attached rcw source code from LSDK 2012 to you, you could refer to&amp;nbsp;ls1046aqds/RR_FFSNPNNN_1133_8888/rcw_1600.rcw to customize your RCW file.&lt;/P&gt;
&lt;P&gt;3. Please refer to the following PBI command in ls1046aqds/RR_FFSNPNNN_1133_8888/rcw_1600.rcw.&lt;/P&gt;
&lt;P&gt;#include &amp;lt;../ls1046ardb/cci_barrier_disable.rcw&amp;gt;&lt;BR /&gt;#include &amp;lt;../ls1046ardb/usb_phy_freq.rcw&amp;gt;&lt;BR /&gt;#include &amp;lt;../ls1046ardb/uboot_address.rcw&amp;gt;&lt;BR /&gt;#include &amp;lt;../ls1046ardb/a008851.rcw&amp;gt;&lt;BR /&gt;#include &amp;lt;../ls1046ardb/a010477.rcw&amp;gt;&lt;BR /&gt;#include &amp;lt;../ls1046ardb/a009531.rcw&amp;gt;&lt;/P&gt;
&lt;P&gt;4. You need to include ls1046ardb/uboot_address.rcw to add the following PBI commands.&lt;/P&gt;
&lt;P&gt;.pbi&lt;BR /&gt;write 0x570600, 0x00000000&lt;BR /&gt;write 0x570604, 0x60100000&lt;BR /&gt;.end&lt;/P&gt;</description>
      <pubDate>Fri, 26 Nov 2021 08:31:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Bare-board-based-on-LS1046ardb-booting-from-NOR-problem/m-p/1377493#M9506</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2021-11-26T08:31:11Z</dc:date>
    </item>
    <item>
      <title>Re: Bare board based on LS1046ardb booting from NOR problem</title>
      <link>https://community.nxp.com/t5/Layerscape/Bare-board-based-on-LS1046ardb-booting-from-NOR-problem/m-p/1377575#M9507</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;thanks for the hints&lt;/P&gt;&lt;P&gt;regarding&lt;/P&gt;&lt;P&gt;1. understood, we build the rcw with eclipse QorIQ, added all PBI commands,&amp;nbsp;&lt;/P&gt;&lt;P&gt;according to ls1046aqds_pbi.cfg, just changed the bootloader entry to 0x6010000&lt;/P&gt;&lt;P&gt;and program separately at 0x60000000&lt;/P&gt;&lt;P&gt;it seems to work, processor accept it and turns off the asleep LED&lt;/P&gt;&lt;P&gt;2. We built the uboot based on SDK20, make ls1046aqds_defconfig, make,&lt;/P&gt;&lt;P&gt;just modified our I2C SPD address to 0x50&lt;/P&gt;&lt;P&gt;program u-boot.bin to 0x6010000, no serial output after power cycle, &lt;LI-EMOJI id="lia_disappointed-face" title=":disappointed_face:"&gt;&lt;/LI-EMOJI&gt;&lt;/P&gt;&lt;P&gt;3. Does the DDR4 has to be initalized before we see the first messages, like this ?&lt;/P&gt;&lt;P&gt;U-Boot 2018.03-00002-gc7a1f2d3e4-dirty (Nov 22 2021 - 16:01:37 +0100)&lt;/P&gt;&lt;P&gt;SoC: LS1046AE Rev1.0 (0x87070010)&lt;/P&gt;&lt;P&gt;we thought DDR init comes later, right ?&lt;/P&gt;&lt;P&gt;4. Don't we need a SPL version of uboot ?&lt;/P&gt;&lt;P&gt;when we boot from SD card, we see a double boot, first with&lt;/P&gt;&lt;P&gt;U-Boot SPL 2018.03-00002-gc7a1f2d3e4-dirty&lt;/P&gt;&lt;P&gt;it inits the DDR and then the bootloader starts again with:&lt;/P&gt;&lt;P&gt;U-Boot 2018.03-00002-gc7a1f2d3e4-dirty&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks for help,&lt;/P&gt;&lt;P&gt;Michael&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 26 Nov 2021 10:18:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Bare-board-based-on-LS1046ardb-booting-from-NOR-problem/m-p/1377575#M9507</guid>
      <dc:creator>micha</dc:creator>
      <dc:date>2021-11-26T10:18:21Z</dc:date>
    </item>
    <item>
      <title>Re: Bare board based on LS1046ardb booting from NOR problem</title>
      <link>https://community.nxp.com/t5/Layerscape/Bare-board-based-on-LS1046ardb-booting-from-NOR-problem/m-p/1379611#M9542</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;problem SOLVED:&amp;nbsp;&lt;/P&gt;&lt;P&gt;we setup a debug session with CodeWarrior TAP and figured out a wrong string at:&lt;/P&gt;&lt;P&gt;CONFIG_DEFAULT_DEVICE_TREE, corrected to:&lt;/P&gt;&lt;P&gt;CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb" and then bootloader starts in NOR.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;just answer myself:&lt;/P&gt;&lt;P&gt;SPL option is not necessary, because processor can run directly from memory-mapped device, the parallel NOR flash&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks again and regards,&lt;/P&gt;&lt;P&gt;Michael&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 01 Dec 2021 10:03:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Bare-board-based-on-LS1046ardb-booting-from-NOR-problem/m-p/1379611#M9542</guid>
      <dc:creator>micha</dc:creator>
      <dc:date>2021-12-01T10:03:35Z</dc:date>
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  </channel>
</rss>

