topic About PCI Express lanes in Layerscape

About PCI Express lanes

okamotosatoshi — Wed, 08 Sep 2021 04:30:52 GMT

Hi There,

We plan to use the LS1043A for in Automotive use.
Use SerDes with SRDS_PRTCL_S1 = 9960.
(A:PCIe(x1)、B:PCIe(x1)、C/D:PCIe(x2))
I want to run an SSD module (PCIex4) with SerDes C/D.

I have some questions on the "LS1043A".

1.Are SerDes C = lane0 and SerDes D = lane1 correct ?

2.Does the PCI controller support 2-lane operation ?
(SSD module (PCIe x 4))

Best regards
- satoshi

Re: About PCI Express lanes

yipingwang — Tue, 14 Sep 2021 01:49:24 GMT

Are SerDes C = lane0 and SerDes D = lane1 correct ?

[NXP] LNmGCR0[FIRST_LANE] --> Indicates the lane is the first (lane 0) of a group of lanes. For the 0x9960 protocol, you will see the value for Lane C as 1'b1 indicating lane 0 of the link, whereas, for lane D, the value will be 1'b0, indicating NOT lane 0 of the link.

Does the PCI controller support a 2-lane operation?

(SSD module (PCIe x 4))

[NXP] Yes, it should work assuming SSD is connected via the SATA-PCIe interface.