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    <title>LayerscapeのトピックRe: QSPI_B in single IO mode(LS1046)</title>
    <link>https://community.nxp.com/t5/Layerscape/QSPI-B-in-single-IO-mode-LS1046/m-p/1335437#M8849</link>
    <description>&lt;P&gt;Use recommendation from the AN5252 Rev 2:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://www.nxp.com/docs/en/application-note/AN5252.pdf" target="_blank"&gt;https://www.nxp.com/docs/en/application-note/AN5252.pdf&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;QSPI_B_DATA[0:2] - The functionality of these signals is determined by the RCW[IFC_GRP_D_EXT] bits of reset configuration word.&lt;/P&gt;
&lt;P&gt;If this pin is not used, it should be programmed as GPIO and output.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;QSPI_B_DATA[3] - The functionality of these signals is determined by the RCW[IFC_GRP_E1_EXT] bits of reset configuration word.&lt;/P&gt;
&lt;P&gt;If this pin is not used, it should be programmed as GPIO and output.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;These pins can be floated also since the Figure 27-2 in the LS1046a Reference Manual shows the following:&lt;/P&gt;
&lt;P&gt;Single Pad Instructions - IOFx[3:2] - Driven all the time to logic level 1&lt;/P&gt;</description>
    <pubDate>Mon, 06 Sep 2021 10:07:10 GMT</pubDate>
    <dc:creator>Pavel</dc:creator>
    <dc:date>2021-09-06T10:07:10Z</dc:date>
    <item>
      <title>QSPI_B in single IO mode(LS1046)</title>
      <link>https://community.nxp.com/t5/Layerscape/QSPI-B-in-single-IO-mode-LS1046/m-p/1335374#M8844</link>
      <description>&lt;P&gt;Hi all,&lt;/P&gt;&lt;P&gt;We are planning to use QSPI-B of LS1046 in single IO mode. It was mentioned in LS1046ARM that QSPI_B_DATA_0 is used as O/P and&amp;nbsp;QSPI_B_DATA_1 is used as I/P in such case. so, my doubt is how shall we terminate the remaining data lines of QSPI_B(DATA_3&amp;amp;4)? can we leave them unconnected as per AN5252?&lt;/P&gt;&lt;P&gt;Thanks in Advance!&lt;/P&gt;</description>
      <pubDate>Mon, 06 Sep 2021 08:51:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/QSPI-B-in-single-IO-mode-LS1046/m-p/1335374#M8844</guid>
      <dc:creator>Urmila_123</dc:creator>
      <dc:date>2021-09-06T08:51:11Z</dc:date>
    </item>
    <item>
      <title>Re: QSPI_B in single IO mode(LS1046)</title>
      <link>https://community.nxp.com/t5/Layerscape/QSPI-B-in-single-IO-mode-LS1046/m-p/1335437#M8849</link>
      <description>&lt;P&gt;Use recommendation from the AN5252 Rev 2:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://www.nxp.com/docs/en/application-note/AN5252.pdf" target="_blank"&gt;https://www.nxp.com/docs/en/application-note/AN5252.pdf&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;QSPI_B_DATA[0:2] - The functionality of these signals is determined by the RCW[IFC_GRP_D_EXT] bits of reset configuration word.&lt;/P&gt;
&lt;P&gt;If this pin is not used, it should be programmed as GPIO and output.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;QSPI_B_DATA[3] - The functionality of these signals is determined by the RCW[IFC_GRP_E1_EXT] bits of reset configuration word.&lt;/P&gt;
&lt;P&gt;If this pin is not used, it should be programmed as GPIO and output.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;These pins can be floated also since the Figure 27-2 in the LS1046a Reference Manual shows the following:&lt;/P&gt;
&lt;P&gt;Single Pad Instructions - IOFx[3:2] - Driven all the time to logic level 1&lt;/P&gt;</description>
      <pubDate>Mon, 06 Sep 2021 10:07:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/QSPI-B-in-single-IO-mode-LS1046/m-p/1335437#M8849</guid>
      <dc:creator>Pavel</dc:creator>
      <dc:date>2021-09-06T10:07:10Z</dc:date>
    </item>
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