LayerscapeのトピックRe: LS1043A

LS1043A

Akshayv — Fri, 06 Aug 2021 05:22:07 GMT

Hi,

In the LS1043A reference design version E, the NXP PMIC used to power enable the LS1043A processor is MC34VR500V4ES.

But, in the revision F of the same reference design the NXP PMIC is changed to MC34VR500VAES.

1. what was the motive to change the NXP PMIC for LS1043A reference design to change from MC34VR500V4ES to MC34VR500VAES..?

2. what would be the part NXP suggest for Power on sequence LS1043A..?

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Thanks & Regards,

Akshay V

Re: LS1043A

Akshayv — Mon, 09 Aug 2021 06:24:34 GMT

please respond and clarify.

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Thanks & Regards,

Akshay V

Re: LS1043A

Bulat — Mon, 09 Aug 2021 10:26:06 GMT

1. Rev F design was slightly optimized to get less power dissipation of the MC34VR500. In rev E design X1VDD was generated by LDO regulator, in revF it is generated by SW2 regulator, this is more efficient solution in terms of power dissipation.

2. Power sequence of both board revisions meet requirements of the LS1043A. We would recommend to follow rev F as up-to-date and power effective one as mentioned above.

Regards,

Bulat

Re: LS1043A

Akshayv — Tue, 10 Aug 2021 03:59:52 GMT

Thanks for the support.

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Thanks& Regards,

Akshay V