<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: Not able to program OTPMK on DevBoard LX2160A in Layerscape</title>
    <link>https://community.nxp.com/t5/Layerscape/Not-able-to-program-OTPMK-on-DevBoard-LX2160A/m-p/1313527#M8545</link>
    <description>&lt;P&gt;There is problem with u-boot. You could read&amp;nbsp;&lt;SPAN&gt;SNVS_HPSR_REG through CCS, please refer to the following procedure to program OTPMK fuse through CCS.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;% delete all&lt;BR /&gt;% config cc cwtap:10.193.20.191&lt;BR /&gt;% ccs::config_server 0 10000&lt;BR /&gt;CodeWarrior TAP executable differs from local file.&lt;BR /&gt;CodeWarrior TAP Boot Loader version 1.0.1&lt;BR /&gt;CodeWarrior TAP OS version 1.0.4&lt;BR /&gt;Sending code to CodeWarrior TAP.........done&lt;BR /&gt;Running package script&lt;BR /&gt;% ccs::config_chain {lx2160a dap}&lt;BR /&gt;% display ccs::get_config_chain&lt;BR /&gt;Chain Position 0: LX2160A&lt;BR /&gt;Chain Position 1: CoreSight ATB Funnel&lt;BR /&gt;Chain Position 2: CoreSight TMC&lt;BR /&gt;Chain Position 3: CoreSight TMC&lt;BR /&gt;Chain Position 4: CoreSight ATB Funnel&lt;BR /&gt;Chain Position 5: CoreSight ATB Funnel&lt;BR /&gt;Chain Position 6: CoreSight ATB Funnel&lt;BR /&gt;Chain Position 7: CoreSight ATB Funnel&lt;BR /&gt;Chain Position 8: CoreSight ATB Funnel&lt;BR /&gt;Chain Position 9: CoreSight TMC&lt;BR /&gt;Chain Position 10: CoreSight TMC&lt;BR /&gt;Chain Position 11: CoreSight CTI&lt;BR /&gt;Chain Position 12: CoreSight CTI&lt;BR /&gt;Chain Position 13: CoreSight CTI&lt;BR /&gt;Chain Position 14: CoreSight ATB Funnel&lt;BR /&gt;Chain Position 15: CoreSight TMC&lt;BR /&gt;Chain Position 16: LSDPAA2&lt;BR /&gt;Chain Position 17: Cortex-A5&lt;BR /&gt;Chain Position 18: Cortex-A5 PMU&lt;BR /&gt;Chain Position 19: z4201Mn3&lt;BR /&gt;Chain Position 20: z4201Mn3&lt;BR /&gt;Chain Position 21: Cortex-A72&lt;BR /&gt;Chain Position 22: CoreSight CTI&lt;BR /&gt;Chain Position 23: Cortex-A72 PMU&lt;BR /&gt;Chain Position 24: Cortex-A72 ETM&lt;BR /&gt;Chain Position 25: Cortex-A72&lt;BR /&gt;Chain Position 26: CoreSight CTI&lt;BR /&gt;Chain Position 27: Cortex-A72 PMU&lt;BR /&gt;Chain Position 28: Cortex-A72 ETM&lt;BR /&gt;Chain Position 29: Cortex-A72&lt;BR /&gt;Chain Position 30: CoreSight CTI&lt;BR /&gt;Chain Position 31: Cortex-A72 PMU&lt;BR /&gt;Chain Position 32: Cortex-A72 ETM&lt;BR /&gt;Chain Position 33: Cortex-A72&lt;BR /&gt;Chain Position 34: CoreSight CTI&lt;BR /&gt;Chain Position 35: Cortex-A72 PMU&lt;BR /&gt;Chain Position 36: Cortex-A72 ETM&lt;BR /&gt;Chain Position 37: Cortex-A72&lt;BR /&gt;Chain Position 38: CoreSight CTI&lt;BR /&gt;Chain Position 39: Cortex-A72 PMU&lt;BR /&gt;Chain Position 40: Cortex-A72 ETM&lt;BR /&gt;Chain Position 41: Cortex-A72&lt;BR /&gt;Chain Position 42: CoreSight CTI&lt;BR /&gt;Chain Position 43: Cortex-A72 PMU&lt;BR /&gt;Chain Position 44: Cortex-A72 ETM&lt;BR /&gt;Chain Position 45: Cortex-A72&lt;BR /&gt;Chain Position 46: CoreSight CTI&lt;BR /&gt;Chain Position 47: Cortex-A72 PMU&lt;BR /&gt;Chain Position 48: Cortex-A72 ETM&lt;BR /&gt;Chain Position 49: Cortex-A72&lt;BR /&gt;Chain Position 50: CoreSight CTI&lt;BR /&gt;Chain Position 51: Cortex-A72 PMU&lt;BR /&gt;Chain Position 52: Cortex-A72 ETM&lt;BR /&gt;Chain Position 53: Cortex-A72&lt;BR /&gt;Chain Position 54: CoreSight CTI&lt;BR /&gt;Chain Position 55: Cortex-A72 PMU&lt;BR /&gt;Chain Position 56: Cortex-A72 ETM&lt;BR /&gt;Chain Position 57: Cortex-A72&lt;BR /&gt;Chain Position 58: CoreSight CTI&lt;BR /&gt;Chain Position 59: Cortex-A72 PMU&lt;BR /&gt;Chain Position 60: Cortex-A72 ETM&lt;BR /&gt;Chain Position 61: Cortex-A72&lt;BR /&gt;Chain Position 62: CoreSight CTI&lt;BR /&gt;Chain Position 63: Cortex-A72 PMU&lt;BR /&gt;Chain Position 64: Cortex-A72 ETM&lt;BR /&gt;Chain Position 65: Cortex-A72&lt;BR /&gt;Chain Position 66: CoreSight CTI&lt;BR /&gt;Chain Position 67: Cortex-A72 PMU&lt;BR /&gt;Chain Position 68: Cortex-A72 ETM&lt;BR /&gt;Chain Position 69: Cortex-A72&lt;BR /&gt;Chain Position 70: CoreSight CTI&lt;BR /&gt;Chain Position 71: Cortex-A72 PMU&lt;BR /&gt;Chain Position 72: Cortex-A72 ETM&lt;BR /&gt;Chain Position 73: Cortex-A72&lt;BR /&gt;Chain Position 74: CoreSight CTI&lt;BR /&gt;Chain Position 75: Cortex-A72 PMU&lt;BR /&gt;Chain Position 76: Cortex-A72 ETM&lt;BR /&gt;Chain Position 77: Cortex-A72&lt;BR /&gt;Chain Position 78: CoreSight CTI&lt;BR /&gt;Chain Position 79: Cortex-A72 PMU&lt;BR /&gt;Chain Position 80: Cortex-A72 ETM&lt;BR /&gt;Chain Position 81: Cortex-A72&lt;BR /&gt;Chain Position 82: CoreSight CTI&lt;BR /&gt;Chain Position 83: Cortex-A72 PMU&lt;BR /&gt;Chain Position 84: Cortex-A72 ETM&lt;BR /&gt;Chain Position 85: DAP&lt;BR /&gt;Chain Position 86: SAP2&lt;BR /&gt;% ccs::display_mem 86 0x1e90014 4 0 4&lt;BR /&gt;+0 +4 +8 +C&lt;BR /&gt;[0x01E90014] 88002B00 80000000 00000000 00000000&lt;BR /&gt;%&lt;BR /&gt;% ccs::write_mem 86 0x1e80234 4 0 0xa29a0b2c&lt;BR /&gt;ccs::write_mem 86 0x1e80238 4 0 0x2c8cd201&lt;BR /&gt;ccs::write_mem 86 0x1e8023c 4 0 0x84027ca8&lt;BR /&gt;ccs::write_mem 86 0x1e80240 4 0 0x8e13c7b9&lt;BR /&gt;ccs::write_mem 86 0x1e80244 4 0 0xa0b9d347&lt;BR /&gt;ccs::write_mem 86 0x1e80248 4 0 0x50ef2622&lt;BR /&gt;ccs::write_mem 86 0x1e8024c 4 0 0x98a92efd&lt;BR /&gt;ccs::write_mem 86 0x1e80250 4 0 0xed53d1c3&lt;BR /&gt;&lt;BR /&gt;% ccs::display_mem 86 0x1e90014 4 0 4&lt;BR /&gt;+0 +4 +8 +C&lt;BR /&gt;[0x01E90014] 80002B00 80000000 00000000 00000000&lt;BR /&gt;% ccs::write_mem 86 0x1e80020 4 0 0x2&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Tue, 27 Jul 2021 03:23:04 GMT</pubDate>
    <dc:creator>yipingwang</dc:creator>
    <dc:date>2021-07-27T03:23:04Z</dc:date>
    <item>
      <title>Not able to program OTPMK on DevBoard LX2160A</title>
      <link>https://community.nxp.com/t5/Layerscape/Not-able-to-program-OTPMK-on-DevBoard-LX2160A/m-p/1313375#M8544</link>
      <description>&lt;P&gt;I'm checking the User guide for LSSDK 20.12 and in the page 306 says:&lt;/P&gt;&lt;P&gt;Enable POVDD on LX2160ARDB:&lt;BR /&gt;• Put J9 to enable PROG_SFP&lt;/P&gt;&lt;P&gt;Program OTPMK&lt;BR /&gt;• Check initial SNVS state&lt;/P&gt;&lt;P&gt;=&amp;gt; md $SNVS_HPSR_REG&lt;BR /&gt;88000900&lt;BR /&gt;OR&lt;BR /&gt;=&amp;gt; md 1e90014&lt;BR /&gt;88000900&lt;/P&gt;&lt;P&gt;The second nibble indicates that the OTPMK is not blown&lt;/P&gt;&lt;P&gt;But if I execute the command, the output is like this:&lt;/P&gt;&lt;P&gt;=&amp;gt; md 1e90014&lt;BR /&gt;01e90014: 00000000 00000000 ........&lt;/P&gt;&lt;P&gt;I also could not find this register (SNVS or 1e90014) in code warrior tool (under Peripherals-&amp;gt;SFP) using JTAG through CWTAP&lt;/P&gt;&lt;P&gt;Does it means my board has the secure boot fused?&lt;/P&gt;</description>
      <pubDate>Mon, 26 Jul 2021 21:44:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Not-able-to-program-OTPMK-on-DevBoard-LX2160A/m-p/1313375#M8544</guid>
      <dc:creator>csr202</dc:creator>
      <dc:date>2021-07-26T21:44:20Z</dc:date>
    </item>
    <item>
      <title>Re: Not able to program OTPMK on DevBoard LX2160A</title>
      <link>https://community.nxp.com/t5/Layerscape/Not-able-to-program-OTPMK-on-DevBoard-LX2160A/m-p/1313527#M8545</link>
      <description>&lt;P&gt;There is problem with u-boot. You could read&amp;nbsp;&lt;SPAN&gt;SNVS_HPSR_REG through CCS, please refer to the following procedure to program OTPMK fuse through CCS.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;% delete all&lt;BR /&gt;% config cc cwtap:10.193.20.191&lt;BR /&gt;% ccs::config_server 0 10000&lt;BR /&gt;CodeWarrior TAP executable differs from local file.&lt;BR /&gt;CodeWarrior TAP Boot Loader version 1.0.1&lt;BR /&gt;CodeWarrior TAP OS version 1.0.4&lt;BR /&gt;Sending code to CodeWarrior TAP.........done&lt;BR /&gt;Running package script&lt;BR /&gt;% ccs::config_chain {lx2160a dap}&lt;BR /&gt;% display ccs::get_config_chain&lt;BR /&gt;Chain Position 0: LX2160A&lt;BR /&gt;Chain Position 1: CoreSight ATB Funnel&lt;BR /&gt;Chain Position 2: CoreSight TMC&lt;BR /&gt;Chain Position 3: CoreSight TMC&lt;BR /&gt;Chain Position 4: CoreSight ATB Funnel&lt;BR /&gt;Chain Position 5: CoreSight ATB Funnel&lt;BR /&gt;Chain Position 6: CoreSight ATB Funnel&lt;BR /&gt;Chain Position 7: CoreSight ATB Funnel&lt;BR /&gt;Chain Position 8: CoreSight ATB Funnel&lt;BR /&gt;Chain Position 9: CoreSight TMC&lt;BR /&gt;Chain Position 10: CoreSight TMC&lt;BR /&gt;Chain Position 11: CoreSight CTI&lt;BR /&gt;Chain Position 12: CoreSight CTI&lt;BR /&gt;Chain Position 13: CoreSight CTI&lt;BR /&gt;Chain Position 14: CoreSight ATB Funnel&lt;BR /&gt;Chain Position 15: CoreSight TMC&lt;BR /&gt;Chain Position 16: LSDPAA2&lt;BR /&gt;Chain Position 17: Cortex-A5&lt;BR /&gt;Chain Position 18: Cortex-A5 PMU&lt;BR /&gt;Chain Position 19: z4201Mn3&lt;BR /&gt;Chain Position 20: z4201Mn3&lt;BR /&gt;Chain Position 21: Cortex-A72&lt;BR /&gt;Chain Position 22: CoreSight CTI&lt;BR /&gt;Chain Position 23: Cortex-A72 PMU&lt;BR /&gt;Chain Position 24: Cortex-A72 ETM&lt;BR /&gt;Chain Position 25: Cortex-A72&lt;BR /&gt;Chain Position 26: CoreSight CTI&lt;BR /&gt;Chain Position 27: Cortex-A72 PMU&lt;BR /&gt;Chain Position 28: Cortex-A72 ETM&lt;BR /&gt;Chain Position 29: Cortex-A72&lt;BR /&gt;Chain Position 30: CoreSight CTI&lt;BR /&gt;Chain Position 31: Cortex-A72 PMU&lt;BR /&gt;Chain Position 32: Cortex-A72 ETM&lt;BR /&gt;Chain Position 33: Cortex-A72&lt;BR /&gt;Chain Position 34: CoreSight CTI&lt;BR /&gt;Chain Position 35: Cortex-A72 PMU&lt;BR /&gt;Chain Position 36: Cortex-A72 ETM&lt;BR /&gt;Chain Position 37: Cortex-A72&lt;BR /&gt;Chain Position 38: CoreSight CTI&lt;BR /&gt;Chain Position 39: Cortex-A72 PMU&lt;BR /&gt;Chain Position 40: Cortex-A72 ETM&lt;BR /&gt;Chain Position 41: Cortex-A72&lt;BR /&gt;Chain Position 42: CoreSight CTI&lt;BR /&gt;Chain Position 43: Cortex-A72 PMU&lt;BR /&gt;Chain Position 44: Cortex-A72 ETM&lt;BR /&gt;Chain Position 45: Cortex-A72&lt;BR /&gt;Chain Position 46: CoreSight CTI&lt;BR /&gt;Chain Position 47: Cortex-A72 PMU&lt;BR /&gt;Chain Position 48: Cortex-A72 ETM&lt;BR /&gt;Chain Position 49: Cortex-A72&lt;BR /&gt;Chain Position 50: CoreSight CTI&lt;BR /&gt;Chain Position 51: Cortex-A72 PMU&lt;BR /&gt;Chain Position 52: Cortex-A72 ETM&lt;BR /&gt;Chain Position 53: Cortex-A72&lt;BR /&gt;Chain Position 54: CoreSight CTI&lt;BR /&gt;Chain Position 55: Cortex-A72 PMU&lt;BR /&gt;Chain Position 56: Cortex-A72 ETM&lt;BR /&gt;Chain Position 57: Cortex-A72&lt;BR /&gt;Chain Position 58: CoreSight CTI&lt;BR /&gt;Chain Position 59: Cortex-A72 PMU&lt;BR /&gt;Chain Position 60: Cortex-A72 ETM&lt;BR /&gt;Chain Position 61: Cortex-A72&lt;BR /&gt;Chain Position 62: CoreSight CTI&lt;BR /&gt;Chain Position 63: Cortex-A72 PMU&lt;BR /&gt;Chain Position 64: Cortex-A72 ETM&lt;BR /&gt;Chain Position 65: Cortex-A72&lt;BR /&gt;Chain Position 66: CoreSight CTI&lt;BR /&gt;Chain Position 67: Cortex-A72 PMU&lt;BR /&gt;Chain Position 68: Cortex-A72 ETM&lt;BR /&gt;Chain Position 69: Cortex-A72&lt;BR /&gt;Chain Position 70: CoreSight CTI&lt;BR /&gt;Chain Position 71: Cortex-A72 PMU&lt;BR /&gt;Chain Position 72: Cortex-A72 ETM&lt;BR /&gt;Chain Position 73: Cortex-A72&lt;BR /&gt;Chain Position 74: CoreSight CTI&lt;BR /&gt;Chain Position 75: Cortex-A72 PMU&lt;BR /&gt;Chain Position 76: Cortex-A72 ETM&lt;BR /&gt;Chain Position 77: Cortex-A72&lt;BR /&gt;Chain Position 78: CoreSight CTI&lt;BR /&gt;Chain Position 79: Cortex-A72 PMU&lt;BR /&gt;Chain Position 80: Cortex-A72 ETM&lt;BR /&gt;Chain Position 81: Cortex-A72&lt;BR /&gt;Chain Position 82: CoreSight CTI&lt;BR /&gt;Chain Position 83: Cortex-A72 PMU&lt;BR /&gt;Chain Position 84: Cortex-A72 ETM&lt;BR /&gt;Chain Position 85: DAP&lt;BR /&gt;Chain Position 86: SAP2&lt;BR /&gt;% ccs::display_mem 86 0x1e90014 4 0 4&lt;BR /&gt;+0 +4 +8 +C&lt;BR /&gt;[0x01E90014] 88002B00 80000000 00000000 00000000&lt;BR /&gt;%&lt;BR /&gt;% ccs::write_mem 86 0x1e80234 4 0 0xa29a0b2c&lt;BR /&gt;ccs::write_mem 86 0x1e80238 4 0 0x2c8cd201&lt;BR /&gt;ccs::write_mem 86 0x1e8023c 4 0 0x84027ca8&lt;BR /&gt;ccs::write_mem 86 0x1e80240 4 0 0x8e13c7b9&lt;BR /&gt;ccs::write_mem 86 0x1e80244 4 0 0xa0b9d347&lt;BR /&gt;ccs::write_mem 86 0x1e80248 4 0 0x50ef2622&lt;BR /&gt;ccs::write_mem 86 0x1e8024c 4 0 0x98a92efd&lt;BR /&gt;ccs::write_mem 86 0x1e80250 4 0 0xed53d1c3&lt;BR /&gt;&lt;BR /&gt;% ccs::display_mem 86 0x1e90014 4 0 4&lt;BR /&gt;+0 +4 +8 +C&lt;BR /&gt;[0x01E90014] 80002B00 80000000 00000000 00000000&lt;BR /&gt;% ccs::write_mem 86 0x1e80020 4 0 0x2&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 27 Jul 2021 03:23:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Not-able-to-program-OTPMK-on-DevBoard-LX2160A/m-p/1313527#M8545</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2021-07-27T03:23:04Z</dc:date>
    </item>
  </channel>
</rss>

