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    <title>LayerscapeのトピックRe: Secure Boot Guide</title>
    <link>https://community.nxp.com/t5/Layerscape/Secure-Boot-Guide/m-p/1303676#M8366</link>
    <description>&lt;P&gt;1. Please generate secure firmware image with the following command.&lt;/P&gt;
&lt;P&gt;$ flex-builder -i mkfw -m ls1012ardb -b qspi -s&lt;/P&gt;
&lt;P&gt;2. Flex-builder has already generated the whole secure firmware image including all images secure headers, you could deploy&amp;nbsp;firmware_ls1012ardb_uboot_qspiboot_secure.img to the target board directly.&lt;/P&gt;
&lt;P&gt;3. No need specific steps.&lt;/P&gt;
&lt;P&gt;4. You could write&amp;nbsp;&lt;STRONG&gt;OTPMK&amp;nbsp;&lt;/STRONG&gt;to fuse array under u-boot.&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;&lt;SPAN&gt;Write OTPMK fuse values on shadow registers&lt;/SPAN&gt;&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;mw.l 1e80234 a29a0b2c&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;mw.l 1e80238 2c8cd201&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;mw.l 1e8023c 84027ca8&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;mw.l 1e80240 8e13c7b9&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;mw.l 1e80244 a0b9d347&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;mw.l 1e80248 50ef2622&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;mw.l 1e8024c 98a92efd&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;mw.l 1e80250 ed53d1c3&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt; Check OTPMK_ZERO and OTPMK_SYNDROME as 0 in SecMon_HP Status Register&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;md 1e90014&lt;/P&gt;
&lt;P&gt;&amp;nbsp; 8&lt;STRONG&gt;0&lt;/STRONG&gt;000900&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Check SFP_SVHESR no parity error.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;md 1e80024&lt;/P&gt;
&lt;P&gt;&amp;nbsp; 00000000&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt; Permanently write OTPMK from the mirror registers into the fuse array&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;mw 1e80020 0x02000000&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;Please program SRKH mirror registers in CodeWarrior CCS environment&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;ccs::config_server 0 10000&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;&lt;SPAN&gt;ccs::config_chain {ls1043a dap sap2}&lt;/SPAN&gt;&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;display ccs::get_config_chain&lt;BR /&gt;#Check Initial SNVS State and Value in SCRATCH Registers&lt;BR /&gt;ccs::display_mem &amp;lt;dap position&amp;gt; 0x1e90014 4 0 4&lt;BR /&gt;ccs::display_mem &amp;lt;dap position&amp;gt; 0x1ee0200 4 0 4&lt;BR /&gt;#Wrie the SRK Hash Value in Mirror Registers&lt;BR /&gt;ccs::write_mem &amp;lt;dap position&amp;gt; 0x1e80254 4 0 &amp;lt;SRKH1&amp;gt;&lt;BR /&gt;ccs::write_mem &amp;lt;dap position&amp;gt; 0x1e80258 4 0 &amp;lt;SRKH2&amp;gt;&lt;BR /&gt;ccs::write_mem &amp;lt;dap position&amp;gt; 0x1e8025c 4 0 &amp;lt;SRKH3&amp;gt;&lt;BR /&gt;ccs::write_mem &amp;lt;dap position&amp;gt; 0x1e80260 4 0 &amp;lt;SRKH4&amp;gt;&lt;BR /&gt;ccs::write_mem &amp;lt;dap position&amp;gt; 0x1e80264 4 0 &amp;lt;SRKH5&amp;gt;&lt;BR /&gt;ccs::write_mem &amp;lt;dap position&amp;gt; 0x1e80268 4 0 &amp;lt;SRKH6&amp;gt;&lt;BR /&gt;ccs::write_mem &amp;lt;dap position&amp;gt; 0x1e8026c 4 0 &amp;lt;SRKH7&amp;gt;&lt;BR /&gt;ccs::write_mem &amp;lt;dap position&amp;gt; 0x1e80270 4 0 &amp;lt;SRKH8&amp;gt;&lt;BR /&gt;#Get the Core Out of Boot Hold-Off&lt;BR /&gt;ccs::write_mem &amp;lt;dap position&amp;gt; 0x1ee00e4 4 0 0x00000001&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;5.&amp;nbsp;SB_EN is set during development stage.&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Wed, 07 Jul 2021 07:01:54 GMT</pubDate>
    <dc:creator>yipingwang</dc:creator>
    <dc:date>2021-07-07T07:01:54Z</dc:date>
    <item>
      <title>Secure Boot Guide</title>
      <link>https://community.nxp.com/t5/Layerscape/Secure-Boot-Guide/m-p/1302912#M8350</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/12881"&gt;@all&lt;/a&gt;,&lt;/P&gt;&lt;P&gt;I'm writing to gather information needed to preform secure boot on LS1012A. LSDK User Guide contains information but is written in&amp;nbsp;ambiguous fashion. There is no strict guide "how to" with steps.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;UNDERSTANDING&lt;/P&gt;&lt;P&gt;2 ways of running secure boot:&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;development mode -&amp;nbsp;&lt;SPAN&gt;Setting the SB_EN bit in the RCW.&lt;/SPAN&gt;&lt;/LI&gt;&lt;LI&gt;&lt;SPAN&gt;production mode -&amp;nbsp;Blowing the Intent To Secure (ITS) fuse.&lt;/SPAN&gt;&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;&lt;SPAN&gt;QUESTIONS:&lt;/SPAN&gt;&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;&lt;SPAN&gt;Which images/binaries should be build? Guide?&lt;/SPAN&gt;&lt;/LI&gt;&lt;LI&gt;&lt;SPAN&gt;Which of them should be signed?&lt;/SPAN&gt;&lt;/LI&gt;&lt;LI&gt;&lt;SPAN&gt;What are steps needed to be preformed in U-boot at first run of secure boot?&lt;/SPAN&gt;&lt;/LI&gt;&lt;LI&gt;&lt;SPAN&gt;Can OTPMK and SRKH be set without using payed IDE tools (CodeWarrior)? Guide?&lt;/SPAN&gt;&lt;/LI&gt;&lt;LI&gt;&lt;SPAN&gt;At what stage is SB_EN set?&lt;/SPAN&gt;&lt;/LI&gt;&lt;/OL&gt;</description>
      <pubDate>Tue, 06 Jul 2021 07:09:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Secure-Boot-Guide/m-p/1302912#M8350</guid>
      <dc:creator>OzTheWizard</dc:creator>
      <dc:date>2021-07-06T07:09:40Z</dc:date>
    </item>
    <item>
      <title>Re: Secure Boot Guide</title>
      <link>https://community.nxp.com/t5/Layerscape/Secure-Boot-Guide/m-p/1303676#M8366</link>
      <description>&lt;P&gt;1. Please generate secure firmware image with the following command.&lt;/P&gt;
&lt;P&gt;$ flex-builder -i mkfw -m ls1012ardb -b qspi -s&lt;/P&gt;
&lt;P&gt;2. Flex-builder has already generated the whole secure firmware image including all images secure headers, you could deploy&amp;nbsp;firmware_ls1012ardb_uboot_qspiboot_secure.img to the target board directly.&lt;/P&gt;
&lt;P&gt;3. No need specific steps.&lt;/P&gt;
&lt;P&gt;4. You could write&amp;nbsp;&lt;STRONG&gt;OTPMK&amp;nbsp;&lt;/STRONG&gt;to fuse array under u-boot.&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;&lt;SPAN&gt;Write OTPMK fuse values on shadow registers&lt;/SPAN&gt;&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;mw.l 1e80234 a29a0b2c&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;mw.l 1e80238 2c8cd201&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;mw.l 1e8023c 84027ca8&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;mw.l 1e80240 8e13c7b9&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;mw.l 1e80244 a0b9d347&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;mw.l 1e80248 50ef2622&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;mw.l 1e8024c 98a92efd&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;mw.l 1e80250 ed53d1c3&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt; Check OTPMK_ZERO and OTPMK_SYNDROME as 0 in SecMon_HP Status Register&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;md 1e90014&lt;/P&gt;
&lt;P&gt;&amp;nbsp; 8&lt;STRONG&gt;0&lt;/STRONG&gt;000900&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Check SFP_SVHESR no parity error.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;md 1e80024&lt;/P&gt;
&lt;P&gt;&amp;nbsp; 00000000&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt; Permanently write OTPMK from the mirror registers into the fuse array&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;mw 1e80020 0x02000000&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;Please program SRKH mirror registers in CodeWarrior CCS environment&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;ccs::config_server 0 10000&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;STRONG&gt;&lt;SPAN&gt;ccs::config_chain {ls1043a dap sap2}&lt;/SPAN&gt;&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;display ccs::get_config_chain&lt;BR /&gt;#Check Initial SNVS State and Value in SCRATCH Registers&lt;BR /&gt;ccs::display_mem &amp;lt;dap position&amp;gt; 0x1e90014 4 0 4&lt;BR /&gt;ccs::display_mem &amp;lt;dap position&amp;gt; 0x1ee0200 4 0 4&lt;BR /&gt;#Wrie the SRK Hash Value in Mirror Registers&lt;BR /&gt;ccs::write_mem &amp;lt;dap position&amp;gt; 0x1e80254 4 0 &amp;lt;SRKH1&amp;gt;&lt;BR /&gt;ccs::write_mem &amp;lt;dap position&amp;gt; 0x1e80258 4 0 &amp;lt;SRKH2&amp;gt;&lt;BR /&gt;ccs::write_mem &amp;lt;dap position&amp;gt; 0x1e8025c 4 0 &amp;lt;SRKH3&amp;gt;&lt;BR /&gt;ccs::write_mem &amp;lt;dap position&amp;gt; 0x1e80260 4 0 &amp;lt;SRKH4&amp;gt;&lt;BR /&gt;ccs::write_mem &amp;lt;dap position&amp;gt; 0x1e80264 4 0 &amp;lt;SRKH5&amp;gt;&lt;BR /&gt;ccs::write_mem &amp;lt;dap position&amp;gt; 0x1e80268 4 0 &amp;lt;SRKH6&amp;gt;&lt;BR /&gt;ccs::write_mem &amp;lt;dap position&amp;gt; 0x1e8026c 4 0 &amp;lt;SRKH7&amp;gt;&lt;BR /&gt;ccs::write_mem &amp;lt;dap position&amp;gt; 0x1e80270 4 0 &amp;lt;SRKH8&amp;gt;&lt;BR /&gt;#Get the Core Out of Boot Hold-Off&lt;BR /&gt;ccs::write_mem &amp;lt;dap position&amp;gt; 0x1ee00e4 4 0 0x00000001&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;5.&amp;nbsp;SB_EN is set during development stage.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 07 Jul 2021 07:01:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Secure-Boot-Guide/m-p/1303676#M8366</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2021-07-07T07:01:54Z</dc:date>
    </item>
    <item>
      <title>Re: Secure Boot Guide</title>
      <link>https://community.nxp.com/t5/Layerscape/Secure-Boot-Guide/m-p/1377809#M9514</link>
      <description>&lt;P&gt;Hi Yiping,&lt;/P&gt;&lt;P&gt;I am trying to study and deploy secure boot in LX2160ardb platform.&amp;nbsp; I am not sure about some descriptions in the guide. Could you help to answer these questions?&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;1. I have no codewarrior at hand, so I add some new codes in bl2_main() fucntion. OPTMK/SRKH registers are written here. It looks work well. If don't care to rebuild bl2 bin file repeatedly, does this method have other potential issue?&amp;nbsp;&lt;/P&gt;&lt;P&gt;2. For the&amp;nbsp;SFP_INGR_REG (&lt;SPAN&gt;1e80020), though the guide says&amp;nbsp; "after writing this register, Fuses will be burnt, which cannot be undo...", my test seems show that I can write to update&amp;nbsp;OPTMK/SRKH register time and again. Is there something wrong in my operation?&amp;nbsp; I always connect the "SFP Power" jumper(j9) in the board when doing test.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;3. Where is the correct position to find the&amp;nbsp; SRKH values? Currently I build the xxx_secure.img with flexbuild and then get the "SRK (Public Key) Hash" information after this build line "Header File Created: ./build/lx2160ardb/release/bl2_sd_sec.pbl".&amp;nbsp; Then I write these SRK value to SRKH registers. Is this correct?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thanks!&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;-Jerry&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sun, 28 Nov 2021 12:49:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Secure-Boot-Guide/m-p/1377809#M9514</guid>
      <dc:creator>GeekFork</dc:creator>
      <dc:date>2021-11-28T12:49:31Z</dc:date>
    </item>
    <item>
      <title>Re: Secure Boot Guide</title>
      <link>https://community.nxp.com/t5/Layerscape/Secure-Boot-Guide/m-p/1922928#M14672</link>
      <description>Hi I've stumbled upon the same issue, I do not have access to CodeWarrior nor to NXP debugger. Was your approach with writing mirror registers in bl2 satisfying?&lt;BR /&gt;Or did you approach the other way?&lt;BR /&gt;&lt;BR /&gt;I would be grateful for any hint, since guys from NXP are not willing to share any reasonable solution that would not require their hardware.</description>
      <pubDate>Thu, 01 Aug 2024 10:48:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Secure-Boot-Guide/m-p/1922928#M14672</guid>
      <dc:creator>pb3</dc:creator>
      <dc:date>2024-08-01T10:48:57Z</dc:date>
    </item>
    <item>
      <title>Re: Secure Boot Guide</title>
      <link>https://community.nxp.com/t5/Layerscape/Secure-Boot-Guide/m-p/1964040#M14939</link>
      <description>&lt;P&gt;“&lt;SPAN&gt;Was your approach with writing mirror registers in bl2 satisfying?&lt;/SPAN&gt;”， yes, this is a way to verify secure boot with&amp;nbsp;&lt;SPAN&gt;SRKH and something else. This is a way in product debug and solution&amp;nbsp; verification period.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sun, 29 Sep 2024 13:23:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Secure-Boot-Guide/m-p/1964040#M14939</guid>
      <dc:creator>GeekFork</dc:creator>
      <dc:date>2024-09-29T13:23:19Z</dc:date>
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