topic DRAM bus speed optimization test ls1021a in Layerscape

DRAM bus speed optimization test ls1021a

winstonjacob — Fri, 18 Jun 2021 12:20:47 GMT

I am using LS1021atwr board, here I need to do the DRAM bus speed optimization, please support me to do this test in LS1021atwr EVK board.

Regards

Winston

Re: DRAM bus speed optimization test ls1021a

Bulat — Mon, 21 Jun 2021 12:54:13 GMT

Please clarify what means "DRAM bus speed optimization"?

Why do you think the DRAM bus speed is not optimized?

Regards

Bulat

Re: DRAM bus speed optimization test ls1021a

winstonjacob — Tue, 29 Jun 2021 07:13:33 GMT

Thanks for your reply @Bulat

Please clarify what means "DRAM bus speed optimization"?

I need to test the DRAM in various frequencies and various speed, is their any procedure available for this.

Regards

Winston

Re: DRAM bus speed optimization test ls1021a

Bulat — Fri, 09 Jul 2021 03:25:30 GMT

Default DDR speed of the LS1021ATWR is 1600MT/s, this is a maximum possible speed for the LS1021A DDR controller. U-boot software provides setup for this speed.

If maximum possible speed is not "optimal" for you, you can test other speeds using DDR Validation tool, that is a part of QCVS. Note that DDR speed is defined by RCW, so for each DDR bus speed you will need to change RCW with desired MEM_PLL_RAT ratio. The tool will help with timing parameters for chosen bus frequency.

Regards,

Bulat