LayerscapeのトピックRe: LS1021a full boot sequence

LS1021a full boot sequence

vsiles — Tue, 26 Apr 2016 07:20:46 GMT

Hi,

I'm trying to understand the full boot sequence of the LS1021a, and I'm a bit confused.

From what I gathered so far from SDK v1.9, the high-level view is:

- PBL code reads the fuses / RCW / PBI commands

- at some point, it copies u-boot from the boot medium to OCRAM and runs it (SD in my case)

- at this point, u-boot can configure DDR, copy Linux into it and boot Linux

What I'm unsure about is:

- Is the PBL executed by Cortex-a7 core 0, or is it an external chip ?

- Is the PBL code located in the ROM section (first Mb of the memory map) ?

- If that's not the case, can we access the PBL code to understand it ?

- In the RCW generated by the SDK (sdcard_ifc), there are lots of PBI instructions which copy code to OCRAM (like TZASC, IFC, SATA config ...) but I don't understand when the control branch to this code.

Best,

Re: LS1021a full boot sequence

alexander_yakov — Fri, 29 Apr 2016 07:26:01 GMT

PBL is executed by PBL block, this block is a separate block in the device, not a part of core.

PBL code is located at attdess, specified in Section 8.5.1 of LS1021A Reference Manual. It depends on the device type you are using for PBL.

Yes, you can access PBL code.

PBL structure is quite simple - number of bytes, address in memory, and bytes itself. PBL block just executes this as sequence, placing requested number of data to requested addersses. This is "pre-boot loader" - it pre-configure specific addresses in memory before starting the core. If you want to start the core from internal OCRAM than you have to pre-load the code to this OCRAM by your pre-boot loader and than release core.

Have a great day,
Alexander

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

Re: LS1021a full boot sequence

vsiles — Fri, 29 Apr 2016 07:56:57 GMT

Ok, I see. If I understand you correctly, the PBL will:

- read the RCW on the selected medium

- copy the RCW in the DCFG registers

- read the PBI from the selected medium

- execute the PBI commands

- jump at the address written in SCRATCHRW1

In case of secure boot (e.g. if RCW says so), does the PBL perform the check of the ESBC's CSL itself or do I have to write code (using PBI or code in ocram for example) to do so ? Basically my question is: in case of secure boot, is there already some code that will check the signature of the ESBC or do I have to write this check using the SEC engine ?

Thank you for all these information,

Best regards,

Vincent