<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>LayerscapeのトピックRe: LS1043A PCIe End point</title>
    <link>https://community.nxp.com/t5/Layerscape/LS1043A-PCIe-End-point/m-p/1272103#M7920</link>
    <description>&lt;P&gt;Please refer to the QorIQ LS1043A Reference Manual, 28.1 The PCI Express controller as implemented on the chip:&lt;/P&gt;
&lt;P&gt;"NOTE&lt;BR /&gt;The EP mode is not supported in LS1043A; any references to that should be ignored."&lt;/P&gt;</description>
    <pubDate>Wed, 05 May 2021 09:17:43 GMT</pubDate>
    <dc:creator>ufedor</dc:creator>
    <dc:date>2021-05-05T09:17:43Z</dc:date>
    <item>
      <title>LS1043A PCIe End point</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1043A-PCIe-End-point/m-p/1272089#M7919</link>
      <description>&lt;P&gt;Can we configure PCIe of&amp;nbsp; LS1043A as End point? If yes, is it with RCW register?&lt;/P&gt;</description>
      <pubDate>Wed, 05 May 2021 08:57:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1043A-PCIe-End-point/m-p/1272089#M7919</guid>
      <dc:creator>SrinivasP</dc:creator>
      <dc:date>2021-05-05T08:57:11Z</dc:date>
    </item>
    <item>
      <title>Re: LS1043A PCIe End point</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1043A-PCIe-End-point/m-p/1272103#M7920</link>
      <description>&lt;P&gt;Please refer to the QorIQ LS1043A Reference Manual, 28.1 The PCI Express controller as implemented on the chip:&lt;/P&gt;
&lt;P&gt;"NOTE&lt;BR /&gt;The EP mode is not supported in LS1043A; any references to that should be ignored."&lt;/P&gt;</description>
      <pubDate>Wed, 05 May 2021 09:17:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1043A-PCIe-End-point/m-p/1272103#M7920</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2021-05-05T09:17:43Z</dc:date>
    </item>
    <item>
      <title>Re: LS1043A PCIe End point</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1043A-PCIe-End-point/m-p/1274217#M7972</link>
      <description>&lt;P&gt;Thank you&lt;/P&gt;</description>
      <pubDate>Mon, 10 May 2021 05:45:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1043A-PCIe-End-point/m-p/1274217#M7972</guid>
      <dc:creator>SrinivasP</dc:creator>
      <dc:date>2021-05-10T05:45:42Z</dc:date>
    </item>
    <item>
      <title>Re: LS1043A PCIe End point</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1043A-PCIe-End-point/m-p/1274218#M7973</link>
      <description>&lt;P&gt;I want to get clarified on one more topic. As per PCIe spec and generation a specified transfer rate is mentioned (2. GT/s , 5 GT/s etc). Is this transfer rate fixed or can we configure any transfer rate below the maximum specified?&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 10 May 2021 05:48:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1043A-PCIe-End-point/m-p/1274218#M7973</guid>
      <dc:creator>SrinivasP</dc:creator>
      <dc:date>2021-05-10T05:48:26Z</dc:date>
    </item>
  </channel>
</rss>

