LayerscapeのトピックRe: How Flash Timing Registers are configured for CPLD connectedon IFC Bus?

How Flash Timing Registers are configured for CPLD connectedon IFC Bus?

winstonjacob — Sat, 03 Apr 2021 06:24:56 GMT

Hi,

We are having LS1021aTWR development board.

Below is the contents of ls1021atwr.h file(u-boot source code).

/* CPLD */

#define CONFIG_SYS_CPLD_BASE 0x7fb00000
#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE

#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
CSPR_PORT_SIZE_8 | \
CSPR_MSEL_GPCM | \
CSPR_V)
#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
CSOR_NOR_NOR_MODE_AVD_NOR | \
CSOR_NOR_TRHZ_80)

/* CPLD Timing parameters for IFC GPCM */
#define CONFIG_SYS_FPGA_FTIM0   (FTIM0_GPCM_TACSE(0xf) | \
                                                                FTIM0_GPCM_TEADC(0xf) | \
                                                                FTIM0_GPCM_TEAHC(0xf))

#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
FTIM1_GPCM_TRAD(0x3f))

#define CONFIG_SYS_FPGA_FTIM2   (FTIM2_GPCM_TCS(0xf) | \
                                                                FTIM2_GPCM_TCH(0xf) | \
                                                                FTIM2_GPCM_TWP(0xff))

#define CONFIG_SYS_FPGA_FTIM3 0x0

How these CPLD timing parameters for IFC GPCM calculated?

Re: How Flash Timing Registers are configured for CPLD connectedon IFC Bus?

ufedor — Sat, 03 Apr 2021 07:40:32 GMT

All relevant IFC timing parameters have maximum values to accommodate any CPLD solution.

Re: How Flash Timing Registers are configured for CPLD connectedon IFC Bus?

winstonjacob — Sat, 03 Apr 2021 09:11:24 GMT

Hi,

In the above case, how the value 0x3f is selected for FTIM1_GPCM_TRAD field of Flash Timing register 1 for CSn - Normal GPCM Mode(IFC_FTIM1_CSn_GPCM)?

Re: How Flash Timing Registers are configured for CPLD connectedon IFC Bus?

ufedor — Sat, 03 Apr 2021 09:56:08 GMT

TRAD.jpg

Re: How Flash Timing Registers are configured for CPLD connectedon IFC Bus?

winstonjacob — Sat, 03 Apr 2021 12:38:31 GMT

I'm using ls1021atwr based custom board. Here SRAM(IS62WV25616EBLL) is connected on IFC bus in GPCM mode. In this case how to configure Flash timing register values for SRAM?

Thanks for your support.

Re: How Flash Timing Registers are configured for CPLD connectedon IFC Bus?

ufedor — Sun, 04 Apr 2021 03:50:58 GMT

Please refer to:

1) QorIQ LS1021A Reference Manual, 24.7.1.1.1 Normal GPCM internal counter-based program operation and 24.7.1.2.1 Normal GPCM internal counter-based read operation containing figures describing IFC timing parameters.

2) the SDRAM datasheet timings.

NOTE: IFC module input clock is equal to LS1021A Platform clock.

Considering above note calculate values of the IFC timing parameters to be in accordance with the SDRAM datasheet.

Re: How Flash Timing Registers are configured for CPLD connectedon IFC Bus?

winstonjacob — Tue, 06 Apr 2021 09:54:20 GMT

In our design SRAM doesn't have clock can you please confirm how to check the SRAM timing and clock sequence in our custom board.

Thanks in Advance.

Re: How Flash Timing Registers are configured for CPLD connectedon IFC Bus?

ufedor — Tue, 06 Apr 2021 16:47:51 GMT

> SRAM doesn't have clock

Please use previously described sequence to determine the IFC timing parameters.