uboot not loading in LS1046

rashmikj — Mon, 22 Mar 2021 04:58:13 GMT

Hi,

I modified ls1046ardb_tfa_defconfig as per our custom board and generated the fip.bin. this is log messages generated.

INFO: RCW BOOT SRC is QSPI
INFO: RCW BOOT SRC is QSPI
INFO: time base 5 ms
NOTICE: Fixed DDR on board
INFO: Time after parsing SPD 4 ms
INFO: Time before programming controller 8 ms
NOTICE: 4 GB DDR4, 64-bit, CL=15, ECC on
INFO: Time used by DDR driver 427 ms
NOTICE: BL2: v1.5(debug):LSDK-20.04-update-290520-dirty
NOTICE: BL2: Built : 09:24:41, Mar 22 2021
INFO: Configuring TrustZone Controller
INFO: Value of region base = ffe00000
INFO: Value of region base = 1ffe00000
INFO: Value of region base = fbe00000
INFO: Value of region base = 980000000
INFO: BL2: Doing platform setup
INFO: BL2: Loading image id 3
INFO: Loading image id=3 at address 0xfbe00000
INFO: Image id=3 loaded: 0xfbe00000 - 0xfbe0c644
INFO: BL2: Loading image id 5
INFO: Loading image id=5 at address 0x82000000
INFO: Image id=5 loaded: 0x82000000 - 0x820b694c
NOTICE: BL2: Booting BL31
INFO: Entry point address = 0xfbe00000
INFO: SPSR = 0x3cd
NOTICE: BL31: v1.5(debug):LSDK-20.04-update-290520-dirty
NOTICE: BL31: Built : 09:20:18, Mar 22 2021
NOTICE: Welcome to LS1046 BL31 Phase
INFO: ARM GICv2 driver initialized
INFO: BL31: Initializing runtime services
WARNING: BL31: cortex_a72: CPU workaround for 859971 was missing!
INFO: BL31: cortex_a72: CPU workaround for cve_2017_5715 was applied
INFO: BL31: cortex_a72: CPU workaround for cve_2018_3639 was applied
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x82000000
INFO: SPSR = 0x3c9

It stops after this . What is the issue. Kindly help.

Re: uboot not loading in LS1046

yipingwang — Tue, 23 Mar 2021 03:36:09 GMT

It seems that there is DDR initialization problem to cause the failing to read u-boot from DDR memory.

Please use QCVS DDRv tool to do DDR configuration parameters optimization and validation. Please create a QCVS DDR project with "read from SPD" method, you could refer to document https://community.nxp.com/t5/Qonverge-Knowledge-Base/DDR-Controller-Configuration-on-LS2085-LS2080-Bringing-up/ta-p/1128310 to do DDRv optimization.

After using DDRv tool to get the optimized DDR controller configuration parameters, please modify atf source code in packages/firmware/atf/.

Please modify the section "const struct ddr_cfg_regs static_1600" in plat/nxp/soc-ls1046/ls1046ardb/ddr_init.c.

In addition please define CONFIG_STATIC_DDR in plat/nxp/soc-ls1046/ls1046ardb/platform_def.h.

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