topic Re: Single Rank UDIMM on LS1046A-RDB in Layerscape

Single Rank UDIMM on LS1046A-RDB

mdecandia — Fri, 05 Mar 2021 09:11:13 GMT

Hi all,

we have replaced the UDIMM on LS1046A-RDB with a single rank 8G UDIMM Kingston KTH-PL424E/8G.

Due to difference in rank size (original Micron 18asf1g72az-2g3b1 was dual rank), U-Boot declares this UDIMM unsupported.

Is this an hardware limit of this EVB? If not, which are the needed changes to apply to U-Boot to support it?

Thanks

Re: Single Rank UDIMM on LS1046A-RDB

Bulat — Fri, 05 Mar 2021 12:28:33 GMT

To be sure what your issue is, can you add u-boot log details?

Re: Single Rank UDIMM on LS1046A-RDB

mdecandia — Fri, 05 Mar 2021 12:49:11 GMT

Here the logs with debug traces enabled

U-Boot 2019.04

initcall: 00000000402188fc
U-Boot code: 40200000 -> 402A1188 BSS: -> 402AA7F0
initcall: 0000000040203628
SoC: LS1046AE Rev1.0 (0x87070010)
Clock Configuration:
CPU0(A72):1600 MHz CPU1(A72):1600 MHz CPU2(A72):1600 MHz
CPU3(A72):1600 MHz
Bus: 600 MHz DDR: 2100 MT/s FMAN: 700 MHz
Reset Configuration Word (RCW):
00000000: 0c150010 0e000000 00000000 00000000
00000010: 11335559 40005012 40025000 c1000000
00000020: 00000000 00000000 00000000 00238800
00000030: 20124000 00003101 00000096 00000001
initcall: 0000000040219190
Model: LS1046A RDB Board
Board: LS1046ARDB, boot from QSPI vBank 2
CPLD: V2.2
PCBA: V2.0
SERDES Reference Clocks:
SD1_CLK1 = 156.25MHZ, SD1_CLK2 = 100.00MHZ
initcall: 0000000040218b20
initcall: 0000000040218930
initcall: 0000000040218af0
I2C: ready
initcall: 0000000040218ad0
DRAM: initcall: 0000000040203ae8
Initializing DDR....using SPD
Detected UDIMM 9965684-012.A00G
DIMM is not supported by this board
resetting ...
initcall: 00000000400831b8

Re: Single Rank UDIMM on LS1046A-RDB

mdecandia — Fri, 05 Mar 2021 12:53:05 GMT

Looking at code the unsupported message comes from this supported udimms:

static const struct board_specific_parameters udimm0[] = {
/*
* memory controller 0
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
{1, 1666, 0, 0x8, 0x0D, 0x0C0B0A08, 0x0A0B0C08,}, // Got from rdimm0
{1, 1900, 0, 0x8, 0x0E, 0x0D0C0B09, 0x0B0C0D09,},
{1, 2300, 0, 0xa, 0x12, 0x100F0D0C, 0x0E0F100C,},
{2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
{2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
{2, 2300, 0, 8, 9, 0x0A0B0C10, 0x1213140E,},
{}
};

in "board/freescale/ls1046ardb/ddr.h"

Re: Single Rank UDIMM on LS1046A-RDB

mdecandia — Fri, 05 Mar 2021 12:55:25 GMT

Making this changes:

diff --git a/board/freescale/ls1046ardb/ddr.h b/board/freescale/ls1046ardb/ddr.h
index 3b4d44d465..f40f483402 100644
--- a/board/freescale/ls1046ardb/ddr.h
+++ b/board/freescale/ls1046ardb/ddr.h
@@ -29,6 +29,9 @@ static const struct board_specific_parameters udimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2 | ctl3
*/
+ {1, 1666, 0, 0x8, 0x0D, 0x0C0B0A08, 0x0A0B0C08,}, // Got from rdimm0
+ {1, 1900, 0, 0x8, 0x0E, 0x0D0C0B09, 0x0B0C0D09,},
+ {1, 2300, 0, 0xa, 0x12, 0x100F0D0C, 0x0E0F100C,},
{2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
{2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
{2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},

ports me here:

U-Boot 2019.04

initcall: 0000000040218478
U-Boot code: 40200000 -> 402A7840 BSS: -> 402B0FF0
initcall: 0000000040203628
SoC: LS1046AE Rev1.0 (0x87070010)
Clock Configuration:
CPU0(A72):1600 MHz CPU1(A72):1600 MHz CPU2(A72):1600 MHz
CPU3(A72):1600 MHz
Bus: 600 MHz DDR: 2100 MT/s FMAN: 700 MHz
Reset Configuration Word (RCW):
00000000: 0c150010 0e000000 00000000 00000000
00000010: 11335559 40005012 40025000 c1000000
00000020: 00000000 00000000 00000000 00238800
00000030: 20124000 00003101 00000096 00000001
initcall: 0000000040218d0c
Model: LS1046A RDB Board
Board: LS1046ARDB, boot from QSPI vBank 2
CPLD: V2.2
PCBA: V2.0
SERDES Reference Clocks:
SD1_CLK1 = 156.25MHZ, SD1_CLK2 = 100.00MHZ
initcall: 000000004021869c
initcall: 00000000402184ac
initcall: 000000004021866c
I2C: ready
initcall: 000000004021864c
DRAM: initcall: 0000000040203ae8
Initializing DDR....using SPD
Detected UDIMM 9965684-012.A00G
DDR: selected 2300 mhz for ddr_freq 2100
Found timing match: n_ranks 1, data rate 2300, rank_gb 0
Write to debug_29 as 00600061
Controler 0 timeout, debug_2 = 2100
total 8 GB
Need to wait up to 204 * 10ms
Waiting for D_INIT timeout. Memory may not work.
initcall: 00000000402184ac
initcall: 00000000402184ac
initcall: 00000000402184ac
initcall: 00000000402188d4
Monitor len: 000B0FF0
Ram size: 200000000
Ram top: FBE00000
initcall: 00000000402182f8
initcall: 00000000402184c4
TLB table from fbdf0000 to fbe00000
initcall: 000000004021871c
initcall: 0000000040218724
initcall: 0000000040218410
Reserving 707k for U-Boot at: fbd3f000
initcall: 00000000402183dc
Reserving 1040k for malloc() at: fbc3b000
initcall: 00000000402185f0

Re: Single Rank UDIMM on LS1046A-RDB

mdecandia — Fri, 05 Mar 2021 13:30:24 GMT

changes made to code pasted above

Re: Single Rank UDIMM on LS1046A-RDB

Bulat — Fri, 05 Mar 2021 13:37:33 GMT

I would recommend to use following code instead of 'registered DIMM' options:

{1, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
{1, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,},
{1, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,},
{1, 2300, 0, 8, 9, 0x0A0B0C10, 0x1213140E,},

I would recommed to run DDRv tool to evaluate optimal parameters (that are write leveling ones) for single-rank UDIMM.

Regards,

Bulat

Re: Single Rank UDIMM on LS1046A-RDB

mdecandia — Fri, 05 Mar 2021 13:59:41 GMT

Thanks for the reply. I did already that test and it crashes at same way:

U-Boot 2019.04

initcall: 0000000040218478
U-Boot code: 40200000 -> 402A7858 BSS: -> 402B0FF0
initcall: 0000000040203628
SoC: LS1046AE Rev1.0 (0x87070010)
Clock Configuration:
CPU0(A72):1600 MHz CPU1(A72):1600 MHz CPU2(A72):1600 MHz
CPU3(A72):1600 MHz
Bus: 600 MHz DDR: 2100 MT/s FMAN: 700 MHz
Reset Configuration Word (RCW):
00000000: 0c150010 0e000000 00000000 00000000
00000010: 11335559 40005012 40025000 c1000000
00000020: 00000000 00000000 00000000 00238800
00000030: 20124000 00003101 00000096 00000001
initcall: 0000000040218d0c
Model: LS1046A RDB Board
Board: LS1046ARDB, boot from QSPI vBank 2
CPLD: V2.2
PCBA: V2.0
SERDES Reference Clocks:
SD1_CLK1 = 156.25MHZ, SD1_CLK2 = 100.00MHZ
initcall: 000000004021869c
initcall: 00000000402184ac
initcall: 000000004021866c
I2C: ready
initcall: 000000004021864c
DRAM: initcall: 0000000040203ae8
Initializing DDR....using SPD
Detected UDIMM 9965684-012.A00G
DDR: selected 2300 mhz for ddr_freq 2100
Found timing match: n_ranks 1, data rate 2300, rank_gb 0
Write to debug_29 as 00600061
Controler 0 timeout, debug_2 = 2100
total 8 GB
Need to wait up to 204 * 10ms
Waiting for D_INIT timeout. Memory may not work.
initcall: 00000000402184ac
initcall: 00000000402184ac
initcall: 00000000402184ac
initcall: 00000000402188d4
Monitor len: 000B0FF0
Ram size: 200000000
Ram top: FBE00000
initcall: 00000000402182f8
initcall: 00000000402184c4
TLB table from fbdf0000 to fbe00000
initcall: 000000004021871c
initcall: 0000000040218724
initcall: 0000000040218410
Reserving 707k for U-Boot at: fbd3f000
initcall: 00000000402183dc
Reserving 1040k for malloc() at: fbc3b000
initcall: 00000000402185f0

Re: Single Rank UDIMM on LS1046A-RDB

Bulat — Mon, 08 Mar 2021 05:30:25 GMT

As I wrote, it is quite possible that some parameters are not optimal for single-rank DIMMs, because those were copied from the dual-rank setup. The only way to check is to run DDRv tool and its 'centering the clock' test.

In addition I would add that we have faced with cases when DIMM's SPD was not correct, this can also cause a crash. Our processors require correct DQ mapping information stored in the SPD. If possible, try to test a DIMM from another manufacturer.

Re: Single Rank UDIMM on LS1046A-RDB

mdecandia — Mon, 08 Mar 2021 16:50:52 GMT

Thank you,

I will let you know.