topic Re: Problem with AN12270 in Layerscape

Problem with AN12270

dbexplora — Tue, 26 Jan 2021 15:32:30 GMT

Hi,

We have design a custom board based on the LS1026A. This board will boot from eMMC so we will need to use CodeWarrior TAP probe to program this flash.

The application note AN12270 describe a method to init JTAG, init board DDR, copy the u-boot in the DDR and launch it. We plan to use this method to start our boards and use u-boot commands to write the eMMC.

We have the LS1046ARDB evaluation board and we try to use this method on it without success.

The script always shows a 'Scan timeout' error.

We have modified the lsbp.tcl script as proposed in the AN12270 application note to test if the DDR is working (Chapter 5 Useful Information, point 5 test if DDR is working).

With this modification, we can read LS1046A DDR configuration registers:

(bin) 3 % disp ccs::read_mem 33 0 0x1080000 4 0 32
+0 +4 +8 +C
[0x0000000001080000] FF010000 00000000 FF010000 00000000
[0x0000000001080010] 00000000 00000000 00000000 00000000
[0x0000000001080020] 00000000 00000000 00000000 00000000
[0x0000000001080030] 00000000 00000000 00000000 00000000
[0x0000000001080040] 00000000 00000000 00000000 00000000
[0x0000000001080050] 00000000 00000000 00000000 00000000
[0x0000000001080060] 00000000 00000000 00000000 00000000
[0x0000000001080070] 00000000 00000000 00000000 00000000

But if we read DDR at address 0x82000000, we get an error:

(bin) 4 % disp ccs::read_mem 33 0 0x82000000 4 0 32
Scan timeout
(bin) 5 %

We use the scripts as proposed in the application note (see attached files).

Can you provide some help on that?

Thank you,

Denis

Re: Problem with AN12270

yipingwang — Wed, 27 Jan 2021 03:27:24 GMT

Please try the following command on your target board.

(bin) 4 % delete all
(bin) 5 % config cc cwtap:10.81.116.29
(bin) 6 % show cc
0: CodeWarrior TAP (cwtap:10.81.116.29) CC software ver. {0.0}
(bin) 7 % source IDcode.tcl

Scanning for available TAPs connected via USB.....

No TAPs found connected via USB

++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+ Available Remote Connections
+
+ 1 - CodeWarriorTAP - <Specify IP Address>
+ 2 - GigabitTAP - <Specify IP Address>
+
+ x - Exit Script without Changes
+
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

Specify connection:
1

Specify IP Address

10.81.116.29

Configuring TAP Interface....

Configured Connection: cwtap : 10.81.116.29

TDO -----
|
* Device 0 IDCODE: 5BA00477 Device: ARM DAP rev 5.x
* Device 1 IDCODE: 06B3001D Device: NXP LS1046A rev 1.x
|
TDI -----

###################################################
#
# configTAP - Redefine TAP interface
#
# scanboard - Scans the target system
# and returns the JTAG IDCode
#
# ir - Loopback test
#
###################################################

(bin) 12 % ccs::config_server 0 10000
(bin) 15 % ccs::config_chain {ls1043a dap sap2}
(bin) 16 % display ccs::get_config_chain
Chain Position 0: LS1043A
Chain Position 1: CoreSight ATB Funnel
Chain Position 2: CoreSight ATB Funnel
Chain Position 3: CoreSight TMC
Chain Position 4: CoreSight TMC
Chain Position 5: CoreSight ATB Funnel
Chain Position 6: CoreSight STM
Chain Position 7: CoreSight TMC
Chain Position 8: CoreSight ATB Funnel
Chain Position 9: CoreSight ATB Funnel
Chain Position 10: CoreSight TMC
Chain Position 11: CoreSight TMC
Chain Position 12: CoreSight TMC
Chain Position 13: CoreSight CTI
Chain Position 14: CoreSight CTI
Chain Position 15: CoreSight CTI
Chain Position 16: Cortex-A72
Chain Position 17: CoreSight CTI
Chain Position 18: Cortex-A72 PMU
Chain Position 19: Cortex-A72 ETM
Chain Position 20: Cortex-A72
Chain Position 21: CoreSight CTI
Chain Position 22: Cortex-A72 PMU
Chain Position 23: Cortex-A72 ETM
Chain Position 24: Cortex-A72
Chain Position 25: CoreSight CTI
Chain Position 26: Cortex-A72 PMU
Chain Position 27: Cortex-A72 ETM
Chain Position 28: Cortex-A72
Chain Position 29: CoreSight CTI
Chain Position 30: Cortex-A72 PMU
Chain Position 31: Cortex-A72 ETM
Chain Position 32: DAP
Chain Position 33: SAP2
(bin) 17 % disp ccs::read_mem 33 0 0x1080000 4 0 32
+0 +4 +8 +C
[0x0000000001080000] FF010000 00000000 FF010000 00000000
[0x0000000001080010] 00000000 00000000 00000000 00000000
[0x0000000001080020] 00000000 00000000 00000000 00000000
[0x0000000001080030] 00000000 00000000 00000000 00000000
[0x0000000001080040] 00000000 00000000 00000000 00000000
[0x0000000001080050] 00000000 00000000 00000000 00000000
[0x0000000001080060] 00000000 00000000 00000000 00000000
[0x0000000001080070] 00000000 00000000 00000000 00000000
(bin) 18 % disp ccs::read_mem 33 0 0x82000000 4 0 32
+0 +4 +8 +C
[0x0000000082000000] 1400000A D503201F 82000000 00000000
[0x0000000082000010] 000B6008 00000000 000B6008 00000000
[0x0000000082000020] 000BF880 00000000 14000071 10007EA0
[0x0000000082000030] D5384241 F100303F 540000A0 F100203F
[0x0000000082000040] 54000160 F100103F 540001A0 D51EC000
[0x0000000082000050] D53E1100 B2400C00 D51E1100 D51E115F
[0x0000000082000060] 58000C80 D51BE000 14000008 D51CC000
[0x0000000082000070] D2867FE0 D51C1140 14000004 D518C000
(bin) 19 %

Re: Problem with AN12270

yipingwang — Wed, 27 Jan 2021 04:24:00 GMT

I got the following result after executing lsbp.tcl script in CCS.

(bin) 26 % source lsbp.tcl
(bin) 27 % lsbp::lsbp
Chain Position 0: LS1043A
Chain Position 1: CoreSight ATB Funnel
Chain Position 2: CoreSight ATB Funnel
Chain Position 3: CoreSight TMC
Chain Position 4: CoreSight TMC
Chain Position 5: CoreSight ATB Funnel
Chain Position 6: CoreSight STM
Chain Position 7: CoreSight TMC
Chain Position 8: CoreSight ATB Funnel
Chain Position 9: CoreSight ATB Funnel
Chain Position 10: CoreSight TMC
Chain Position 11: CoreSight TMC
Chain Position 12: CoreSight TMC
Chain Position 13: CoreSight CTI
Chain Position 14: CoreSight CTI
Chain Position 15: CoreSight CTI
Chain Position 16: Cortex-A72
Chain Position 17: CoreSight CTI
Chain Position 18: Cortex-A72 PMU
Chain Position 19: Cortex-A72 ETM
Chain Position 20: Cortex-A72
Chain Position 21: CoreSight CTI
Chain Position 22: Cortex-A72 PMU
Chain Position 23: Cortex-A72 ETM
Chain Position 24: Cortex-A72
Chain Position 25: CoreSight CTI
Chain Position 26: Cortex-A72 PMU
Chain Position 27: Cortex-A72 ETM
Chain Position 28: Cortex-A72
Chain Position 29: CoreSight CTI
Chain Position 30: Cortex-A72 PMU
Chain Position 31: Cortex-A72 ETM
Chain Position 32: DAP
Chain Position 33: SAP2
(bin) 28 % disp ccs::read_mem 33 0 0x1080000 4 0 32
+0 +4 +8 +C
[0x0000000001080000] FF010000 00000000 FF010000 00000000
[0x0000000001080010] 00000000 00000000 00000000 00000000
[0x0000000001080020] 00000000 00000000 00000000 00000000
[0x0000000001080030] 00000000 00000000 00000000 00000000
[0x0000000001080040] 00000000 00000000 00000000 00000000
[0x0000000001080050] 00000000 00000000 00000000 00000000
[0x0000000001080060] 00000000 00000000 00000000 00000000
[0x0000000001080070] 00000000 00000000 00000000 00000000
(bin) 29 % disp ccs::read_mem 33 0 0x82000000 4 0 32
+0 +4 +8 +C
[0x0000000082000000] DEADBEEF DEADBEEF DEADBEEF DEADBEEF
[0x0000000082000010] DEADBEEF DEADBEEF DEADBEEF DEADBEEF
[0x0000000082000020] DEADBEEF DEADBEEF DEADBEEF DEADBEEF
[0x0000000082000030] DEADBEEF DEADBEEF DEADBEEF DEADBEEF
[0x0000000082000040] DEADBEEF DEADBEEF DEADBEEF DEADBEEF
[0x0000000082000050] DEADBEEF DEADBEEF DEADBEEF DEADBEEF
[0x0000000082000060] DEADBEEF DEADBEEF DEADBEEF DEADBEEF
[0x0000000082000070] DEADBEEF DEADBEEF DEADBEEF DEADBEEF
(bin) 30 %

Re: Problem with AN12270

dbexplora — Wed, 27 Jan 2021 12:27:33 GMT

Hi yipingwang, thank you for your support.

I have tried the 2 tests you proposed. Here are the results:

(bin) 1 % delete all
(bin) 2 % config cc cwtap:00:04:9f:06:e0:a2
(bin) 3 % show cc
0: CodeWarrior TAP (cwtap:00:04:9f:06:e0:a2) CC software ver. {0.0}
(bin) 4 % source IDcode.tcl

Scanning for available TAPs connected via USB.....

++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+ Available Remote Connections
+
+ 1 - CodeWarriorTAP - 00:04:9f:06:e0:a2
+ 2 - CodeWarriorTAP - <Specify IP Address>
+ 3 - GigabitTAP - <Specify IP Address>
+
+ x - Exit Script without Changes
+
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

Specify connection:
1

Configuring TAP Interface....

Configured Connection: cwtap : 00:04:9f:06:e0:a2

TDO -----
|
* Device 0 IDCODE: 5BA00477 Device: ARM DAP rev 5.x
* Device 1 IDCODE: 06B3001D Device: NXP LS1046A rev 1.x
|
TDI -----

(bin) 5 % ccs::config_server 0 10000
(bin) 6 % ccs::config_chain {ls1043a dap sap2}
(bin) 7 % display ccs::get_config_chain
Chain Position 0: LS1043A
Chain Position 1: CoreSight ATB Funnel
Chain Position 2: CoreSight ATB Funnel
Chain Position 3: CoreSight TMC
Chain Position 4: CoreSight TMC
Chain Position 5: CoreSight ATB Funnel
Chain Position 6: CoreSight STM
Chain Position 7: CoreSight TMC
Chain Position 8: CoreSight ATB Funnel
Chain Position 9: CoreSight ATB Funnel
Chain Position 10: CoreSight TMC
Chain Position 11: CoreSight TMC
Chain Position 12: CoreSight TMC
Chain Position 13: CoreSight CTI
Chain Position 14: CoreSight CTI
Chain Position 15: CoreSight CTI
Chain Position 16: Cortex-A72
Chain Position 17: CoreSight CTI
Chain Position 18: Cortex-A72 PMU
Chain Position 19: Cortex-A72 ETM
Chain Position 20: Cortex-A72
Chain Position 21: CoreSight CTI
Chain Position 22: Cortex-A72 PMU
Chain Position 23: Cortex-A72 ETM
Chain Position 24: Cortex-A72
Chain Position 25: CoreSight CTI
Chain Position 26: Cortex-A72 PMU
Chain Position 27: Cortex-A72 ETM
Chain Position 28: Cortex-A72
Chain Position 29: CoreSight CTI
Chain Position 30: Cortex-A72 PMU
Chain Position 31: Cortex-A72 ETM
Chain Position 32: DAP
Chain Position 33: SAP2
(bin) 8 % disp ccs::read_mem 33 0 0x1080000 4 0 32
+0 +4 +8 +C
[0x0000000001080000] FF030000 00000000 FF030000 00000000
[0x0000000001080010] 00000000 00000000 00000000 00000000
[0x0000000001080020] 00000000 00000000 00000000 00000000
[0x0000000001080030] 00000000 00000000 00000000 00000000
[0x0000000001080040] 00000000 00000000 00000000 00000000
[0x0000000001080050] 00000000 00000000 00000000 00000000
[0x0000000001080060] 00000000 00000000 00000000 00000000
[0x0000000001080070] 00000000 00000000 00000000 00000000
(bin) 9 % disp ccs::read_mem 33 0 0x82000000 4 0 32
+0 +4 +8 +C
[0x0000000082000000] 1400000A D503201F 82000000 00000000
[0x0000000082000010] 000ADF48 00000000 000ADF48 00000000
[0x0000000082000020] 000B77E8 00000000 14000071 10007EA0
[0x0000000082000030] D5384241 F100303F 540000A0 F100203F
[0x0000000082000040] 54000160 F100103F 540001A0 D51EC000
[0x0000000082000050] D53E1100 B2400C00 D51E1100 D51E115F
[0x0000000082000060] 58000C80 D51BE000 14000008 D51CC000
[0x0000000082000070] D2867FE0 D51C1140 14000004 D518C000
(bin) 10 % source lsbp.tcl
(bin) 11 % lsbp::lsbp
Chain Position 0: LS1043A
Chain Position 1: CoreSight ATB Funnel
Chain Position 2: CoreSight ATB Funnel
Chain Position 3: CoreSight TMC
Chain Position 4: CoreSight TMC
Chain Position 5: CoreSight ATB Funnel
Chain Position 6: CoreSight STM
Chain Position 7: CoreSight TMC
Chain Position 8: CoreSight ATB Funnel
Chain Position 9: CoreSight ATB Funnel
Chain Position 10: CoreSight TMC
Chain Position 11: CoreSight TMC
Chain Position 12: CoreSight TMC
Chain Position 13: CoreSight CTI
Chain Position 14: CoreSight CTI
Chain Position 15: CoreSight CTI
Chain Position 16: Cortex-A72
Chain Position 17: CoreSight CTI
Chain Position 18: Cortex-A72 PMU
Chain Position 19: Cortex-A72 ETM
Chain Position 20: Cortex-A72
Chain Position 21: CoreSight CTI
Chain Position 22: Cortex-A72 PMU
Chain Position 23: Cortex-A72 ETM
Chain Position 24: Cortex-A72
Chain Position 25: CoreSight CTI
Chain Position 26: Cortex-A72 PMU
Chain Position 27: Cortex-A72 ETM
Chain Position 28: Cortex-A72
Chain Position 29: CoreSight CTI
Chain Position 30: Cortex-A72 PMU
Chain Position 31: Cortex-A72 ETM
Chain Position 32: DAP
Chain Position 33: SAP2
(bin) 12 % disp ccs::read_mem 33 0 0x1080000 4 0 32
+0 +4 +8 +C
[0x0000000001080000] FF010000 00000000 FF010000 00000000
[0x0000000001080010] 00000000 00000000 00000000 00000000
[0x0000000001080020] 00000000 00000000 00000000 00000000
[0x0000000001080030] 00000000 00000000 00000000 00000000
[0x0000000001080040] 00000000 00000000 00000000 00000000
[0x0000000001080050] 00000000 00000000 00000000 00000000
[0x0000000001080060] 00000000 00000000 00000000 00000000
[0x0000000001080070] 00000000 00000000 00000000 00000000
(bin) 13 % disp ccs::read_mem 33 0 0x82000000 4 0 32
Scan timeout
(bin) 14 %

Access to 0x82000000 (DDR) is broken after the call to proc lsbp::rcw-override.

Did you use the lsbp.tcl script that we have attached or your own one?

Denis

Re: Problem with AN12270

yipingwang — Thu, 28 Jan 2021 04:49:17 GMT

I used the script attached by you.

You could comment the sentence to configure the target board to use hard-coded RCW in lsbp.tcl to check whether it is possible to read DDR memory.

# Call rcw-override procedure
# lsbp::rcw-override $dut $hardcode_rcw

Are you using LS1046ARDB demo board or your custom board? Probably DDR configurations in the script ddr-init-ls1046rdb.tcl is not suitable for your target board.

Re: Problem with AN12270

dbexplora — Thu, 28 Jan 2021 13:30:11 GMT

We are using the demo board LS1046ARDB.

We have to comment RCW override and DDR init to be able to read from 0x82000000 area:

# Call rcw-override procedure
# lsbp::rcw-override $dut $hardcode_rcw

# Parse the JTAG to find out the chain position of DAP, SAP2, Boot Core
set tap [lsbp::tap-parse]
set dap [lindex $tap 0]
set sap2 [lindex $tap 1]
set boot_core [lindex $tap 2]

# Call the pbi procedure to write minimal registers
lsbp::pbi $dut $dap

# Call init-ddrc procedure to initialize DDR controller
# lsbp::init-ddrc $dap

Just a remark: we have build a u-boot from LSDK20.04. We had to modify the code because the UDIMM on our LS1046ARDB board was not supported.

Denis

Re: Problem with AN12270

yipingwang — Fri, 29 Jan 2021 02:30:29 GMT

You need to modify DDR controller configuration in ddr-init-ls1046rdb.tcl according to your target board.

Re: Problem with AN12270

dbexplora — Mon, 01 Feb 2021 12:31:42 GMT

Our target board is a demo board LS1046ARDB that we bought from NXP... The UDIMM is the one that was installed on the board when we received it.

The DDR initialization that we used is the one provided in the AN12270 application note. We understand that you used the script files that we provided to you and they are working on your LS1046ARDB board. That's right?

Do you know if LS1046ARDB board has been produced with some revisions that could not work with proposed initialization scripts? Can it be caused by a different UDIMM (provided by NXP with the board)?

Thank you.

Re: Problem with AN12270

dbexplora — Wed, 03 Feb 2021 12:31:52 GMT

Hi,

As stated in our last answer, the DDR is the one provided with the LS1046ARDB board we bought from NXP.

If we understand well your last answer, the scan timeout we got is caused by bad DDR configuration. We were more expecting that reading from DDR give bad data rather than cause a scan timeout error.

A last question about that, please, could you tell us why if we comment the DDR configuration from the script (the DDR is correctly configured by the boot loader) and keep the call to the lsbp::rcwoverride function, we still have the scan timeout error?

Thank you.

Re: Problem with AN12270

yipingwang — Mon, 08 Feb 2021 07:56:16 GMT

I used LS1046ARDB with UDIMM 18ASF1G72AZ-2G6B1, please check whether the same UDIMM is integrated on your LS1046ARDB demo board.

Re: Problem with AN12270

dbexplora — Tue, 09 Feb 2021 12:32:40 GMT

Hi, the UDIMM delivered with our LS1046ARDB is UDIMM 18ADF2G72AZ-2G6E1.

Re: Problem with AN12270

yipingwang — Tue, 23 Feb 2021 09:15:39 GMT

It seems that u-boot works well on your target board, you could use "read from target" method to create a QCVS DDRC project from File->New->QorIQ Configuration Project in CodeWarrior IDE, then refer to file ddrCtrl_1.py under Generated_Code to modify the script ddr-init-ls1046rdb.tcl.