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    <title>LayerscapeのトピックLX2160 PCIe Compliance Testing</title>
    <link>https://community.nxp.com/t5/Layerscape/LX2160-PCIe-Compliance-Testing/m-p/1204138#M7269</link>
    <description>&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;We are undertaking PCIe physical layer compliance testing on an LX2160, we are able to interface the PCIe interface (as RC) to a Gen3 device (EP) and communicate at Gen3 speeds however we aren't able to force the link to Gen3 during compliance testing.&lt;/P&gt;&lt;P&gt;During compliance testing we are only able to get Gen1 and Gen2 working for RX/TX, we will attempt forcing the links using the&amp;nbsp;Link Control 2 Register in the PCI RC.&amp;nbsp; Reading the link capabilities register returns that Gen1, Gen2 and Gen3 are all supported however the Link Control 2 register shows only Gen1 and Gen2.&lt;/P&gt;&lt;P&gt;As a further update we have attempted setting the link control 2 register for Gen1, Gen2 and Gen3 and set the compliance bit however doing so meant the link only stayed at Gen1.&lt;/P&gt;&lt;P&gt;To do this we set the the link control 2 register to 0x0017, compliance bit set and bits 0..2 set high for Gen1..Gen3, at reset the link control 2 register reads as 0x0003.&lt;/P&gt;&lt;P&gt;The testing is being performed using the PCISIG Compliance Base Board (CBB) and we are interfacing to LX2160 SERDES 3[0..3] with a PCIe Gen3 M.2 interface, the first Gen1 and Gen2 toggles on the CBB are working, moving to the Gen3 toggle doesn't change to Gen3 as expected.&amp;nbsp; Our PCIe interface does not use lane reversal or polarity inversion.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Would you please provide the correct sequence/register settings for entering PCIe Gen3 compliance with this setup so we can proceed with the compliance testing.&amp;nbsp; The system is running Linux and we are able to modify the registers if required.&lt;/P&gt;&lt;P&gt;Additionally, for the PCIe receiver test, we need to allow for far-end retimed loopback training...which is the standard loopback used for PCIe RX testing, so if additional setup is required for this to work please advise.&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;Malcolm&lt;/P&gt;</description>
    <pubDate>Mon, 04 Jan 2021 16:41:14 GMT</pubDate>
    <dc:creator>HW_Team</dc:creator>
    <dc:date>2021-01-04T16:41:14Z</dc:date>
    <item>
      <title>LX2160 PCIe Compliance Testing</title>
      <link>https://community.nxp.com/t5/Layerscape/LX2160-PCIe-Compliance-Testing/m-p/1204138#M7269</link>
      <description>&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;We are undertaking PCIe physical layer compliance testing on an LX2160, we are able to interface the PCIe interface (as RC) to a Gen3 device (EP) and communicate at Gen3 speeds however we aren't able to force the link to Gen3 during compliance testing.&lt;/P&gt;&lt;P&gt;During compliance testing we are only able to get Gen1 and Gen2 working for RX/TX, we will attempt forcing the links using the&amp;nbsp;Link Control 2 Register in the PCI RC.&amp;nbsp; Reading the link capabilities register returns that Gen1, Gen2 and Gen3 are all supported however the Link Control 2 register shows only Gen1 and Gen2.&lt;/P&gt;&lt;P&gt;As a further update we have attempted setting the link control 2 register for Gen1, Gen2 and Gen3 and set the compliance bit however doing so meant the link only stayed at Gen1.&lt;/P&gt;&lt;P&gt;To do this we set the the link control 2 register to 0x0017, compliance bit set and bits 0..2 set high for Gen1..Gen3, at reset the link control 2 register reads as 0x0003.&lt;/P&gt;&lt;P&gt;The testing is being performed using the PCISIG Compliance Base Board (CBB) and we are interfacing to LX2160 SERDES 3[0..3] with a PCIe Gen3 M.2 interface, the first Gen1 and Gen2 toggles on the CBB are working, moving to the Gen3 toggle doesn't change to Gen3 as expected.&amp;nbsp; Our PCIe interface does not use lane reversal or polarity inversion.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Would you please provide the correct sequence/register settings for entering PCIe Gen3 compliance with this setup so we can proceed with the compliance testing.&amp;nbsp; The system is running Linux and we are able to modify the registers if required.&lt;/P&gt;&lt;P&gt;Additionally, for the PCIe receiver test, we need to allow for far-end retimed loopback training...which is the standard loopback used for PCIe RX testing, so if additional setup is required for this to work please advise.&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;Malcolm&lt;/P&gt;</description>
      <pubDate>Mon, 04 Jan 2021 16:41:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LX2160-PCIe-Compliance-Testing/m-p/1204138#M7269</guid>
      <dc:creator>HW_Team</dc:creator>
      <dc:date>2021-01-04T16:41:14Z</dc:date>
    </item>
    <item>
      <title>Re: LX2160 PCIe Compliance Testing</title>
      <link>https://community.nxp.com/t5/Layerscape/LX2160-PCIe-Compliance-Testing/m-p/1207258#M7316</link>
      <description>&lt;P&gt;The issue investigation will be convenient to perform as a Technical Case.&lt;/P&gt;
&lt;P&gt;Please create a Case and attach all relevant documents:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://support.nxp.com/s/" target="_blank"&gt;https://support.nxp.com/s/&lt;/A&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 06 Jan 2021 05:23:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LX2160-PCIe-Compliance-Testing/m-p/1207258#M7316</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2021-01-06T05:23:45Z</dc:date>
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