LS1027A with DDR3L

igor_franco — Tue, 22 Dec 2020 10:49:23 GMT

Hello,

We are developing a custom board based on the LS1027A processor. We used the LS1028ARDB as an evaluation board to understand the functionality of the LS family. The kit uses four DDR4 of 1GB and another one as ECC. In our custom board, we want to use DDR3L instead of DDR4 (with ECC). According to the "Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces" (AN5097), the DQ swapping must consider the nibble:

igor_franco_0-1608633263975.png

However, when we read the "Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces" (AN3940, identified in chapter 3.1 of "QorIQ LS1028A Design Checklist", AN12028), it says that the swapping can be performed in a byte:

igor_franco_1-1608634005148.png

My question is: how can I configure the DQ mapping register x (DDR_DQ_MAPx) to allows the swap inside a byte once it considers only nibbles? Is this register ignored with DDR3L?

Thank you in advance,

Igor

Re: LS1027A with DDR3L

ufedor — Tue, 22 Dec 2020 13:15:01 GMT

> Is this register ignored with DDR3L?

DQ mapping is applicable for DDR4 SDRAM only.

For DDR3L DQn_MAP registers can be left with default values.

Re: LS1027A with DDR3L

igor_franco — Tue, 22 Dec 2020 13:33:26 GMT

Thank you for the fast answer ufedor.

I marked it as solved.

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LS1027A with DDR3L

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Re: LS1027A with DDR3L