topic Re: How to resolve Synchronous Abort handler issue? in Layerscape

How to resolve Synchronous Abort handler issue?

naveennvn — Thu, 28 Jan 2016 04:56:07 GMT

Hi all,

I'm using LS2085AQDS Board with EAR5 images.

Default images only i flashed. Sometimes in uboot it throws synchronous abort handler error prints and hanging there itself. If i restart after sometime, its working fine.

Per day it throws 4 to 5 times. This is because my work is getting delay.

I want to know why this error is occured and how to resolve it ?. I tried to trace in uboot code. But i can't get exact reason of that.

If anyone know about this issue. Please help me on this.

Boot log is as follows (error ptint is highlighted):

===========================================================================

U-Boot 2015.07-rc1Layerscape2-SDK+gfaa9145 (Dec 21 2015 - 15:34:49)

SoC: LS2085E (0x87010010)

Clock Configuration:

CPU0(A57):1600 MHz CPU1(A57):1600 MHz CPU2(A57):1600 MHz

CPU3(A57):1600 MHz CPU4(A57):1600 MHz CPU5(A57):1600 MHz

CPU6(A57):1600 MHz CPU7(A57):1600 MHz

Bus: 600 MHz DDR: 1333.333 MT/s DP-DDR: 1333.333 MT/s

Reset Configuration Word (RCW):

00: 40282830 40400040 00000000 00000000

10: 00000000 00200000 00200000 00000000

20: 0c212980 00002580 00000000 00000000

30: 00000a08 00000000 00000080 00000080

40: 00000000 00000000 00000000 00000000

50: 00000000 00000000 00000000 00000000

60: 00000000 00000000 00027000 00000000

70: 3f350000 00000000 00000000 00000000

Model: Freescale Layerscape 2085a QDS Board

I2C: ready

Board Arch: V1, Board Version: A

CPLD Version: A10

DRAM: Initializing DDR....using SPD

Detected UDIMM 18ASF1G72HZ-2G1A1

15.5 GiB

DDR 15.5 GiB (DDR4, 64-bit, CL=9, ECC on)

DDR Controller Interleaving Mode: 256B

DDR Chip-Select Interleaving Mode: CS0+CS1

"Synchronous Abort" handler, esr 0x86000210

ELR: fff21180

LR: fff24858

x0 : 00000000fff92a00 x1 : 00000000fff929d0

x2 : 0000000000000040 x3 : 000000000000003f

x4 : 00000000fff8bb64 x5 : 000000004f790d52

x6 : 0000000000000000 x7 : 0000000000000000

x8 : 00000000ffffffff x9 : 00000000cff01000

x10: 0000000000000000 x11: 0000000000000000

x12: 0000000000000000 x13: 0000000000000000

x14: 0000000000000000 x15: 0000000000000000

x16: 0000000000000000 x17: 0000000000000002

x18: 00000000ffd1cd80 x19: 00000000fffb4f58

x20: 0000000000000000 x21: 00000000fff7f4ac

x22: 00000000fff90000 x23: 00000000fff8bc69

x24: 0000000000000001 x25: 0000000000000001

x26: 00000000fff90790 x27: 0000000000000000

x28: 00000000fff75738 x29: 000000003002008c

Resetting CPU ...

### ERROR ### Please RESET the board ###

===================================================================================

Thanks,

-Naveen

Re: How to resolve Synchronous Abort handler issue?

Pavel — Mon, 01 Feb 2016 07:30:47 GMT

Usually similar behavior happens if incorrect DDR setting is used on this board. Restart after sometime and since it happens throws 4 to 5 times, usually shows that some DDR setting is not fully correct for your board.

Try to test your board using different timing parameters for your board.

Test your DDR setting using Double Data Rate RAM Memory Validation (DDRV) or CodeWarrior Development Software for ARM v8 64-bit based QorIQ LS-Series Processors.

CodeWarrior Development Software for ARM v8 64-bit based QorIQ LS-Series Processors includes Double Data Rate RAM Memory Validation (DDRV).

Use the following pages:

https://nxp.flexnetoperations.com/control/frse/download?agree=Accept&element=7308947

https://nxp.flexnetoperations.com/control/frse/download?agree=Accept&element=6121481

Have a great day,
Pavel

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Re: How to resolve Synchronous Abort handler issue?

xiexn — Thu, 27 Dec 2018 01:04:37 GMT

Hi, I have the same issue.

My MCU is S32V234, and use two MT41K512M16HA-125 as the DDR.

What the configurations should be?