topic Re: LS1046A DDR4 Hyperlynx simulation in Layerscape

LS1046A DDR4 Hyperlynx simulation

moshemarcu — Mon, 18 May 2020 06:35:54 GMT

Hi,

I am using LS1046A and I am trying to simulate its DDR4 interface (at 2100MT/s) using Hyperlynx of Mentor.

I am a bit confused regarding filling two parameters for the controller (LS1046A) for the Read cycles.

The Hyperlynx requires two parameters, TDIVW (RX mask) and TDIPW (minimum required pulse width)

The datasheet gives only TCISKEW (±80ps).

Does the TCISKEW equivalent to the TDIVW? What values should I fill for those 2 parameters?

Thanks,

Moshe

Re: LS1046A DDR4 Hyperlynx simulation

Bulat — Mon, 18 May 2020 16:23:17 GMT

DDR controller requires minimum data input valid window to be equal to tCISKEWmax - tCISKEWmin, for 2100MT/S it is 160ps.

Regards,

Bulat

Re: LS1046A DDR4 Hyperlynx simulation

moshemarcu — Mon, 18 May 2020 18:31:40 GMT

Hi,

Thanks for the answer,

Does the valid window need to be centered relative to the DQS? Does the LS1046A support read leveling?

Best regards,

Moshe

Re: LS1046A DDR4 Hyperlynx simulation

Bulat — Wed, 20 May 2020 09:09:30 GMT

Yes, the LS1046A supports read leveling. No special actions like "centering" is required, the LS1046A performs all required calibrations internally.

Regards,

Bulat

Re: LS1046A DDR4 Hyperlynx simulation

moshemarcu — Wed, 20 May 2020 14:51:21 GMT

Hello Bulat,

What kind of read leveling does the LS1046A supports?

Does each DQ can be individually delayed to optimize it with respect to the DQS or

only the DQS signal can be adjusted to optimize it to all the DQ signals?

I could not find any information regarding the read leveling support in the reference manual, how do I configure the LS1046A to activate this process?

Best regards,

Moshe

Re: LS1046A DDR4 Hyperlynx simulation

Bulat — Wed, 20 May 2020 16:12:01 GMT

Read leveling assumes that the DDR controller calibrates the time when the DQS comes from the SDRAM, and then shifts DQS to the center of the data valid window. This is done individually for each byte lane after the DDR controller is enabled with MEM_EN=1. No individual DQ delays, the user must follow DDR4 layout rules, for 2100MT/s rate DQ signals should be trace-matched within +/-5 mils to respective DQS.

Regards,

Bulat

Re: LS1046A DDR4 Hyperlynx simulation

moshemarcu — Thu, 21 May 2020 05:28:47 GMT

Thanks,

Moshe