<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic LS1043A DDR3L data-bit swap in Layerscape</title>
    <link>https://community.nxp.com/t5/Layerscape/LS1043A-DDR3L-data-bit-swap/m-p/1091339#M6445</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I have a question regarding data-bit swap within byte-lan in combination with write levelling for the LS1043A&lt;/P&gt;&lt;P&gt;Does write level support mean the DQ0 pin cannot be swapped? Or is the functionality supported on all pins.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If memory device also matters, we plan to use: Micron&amp;nbsp;MT41K512M16&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;best regards,&lt;/P&gt;&lt;P&gt;Tom&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 13 Aug 2020 10:42:27 GMT</pubDate>
    <dc:creator>tom_derks</dc:creator>
    <dc:date>2020-08-13T10:42:27Z</dc:date>
    <item>
      <title>LS1043A DDR3L data-bit swap</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1043A-DDR3L-data-bit-swap/m-p/1091339#M6445</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I have a question regarding data-bit swap within byte-lan in combination with write levelling for the LS1043A&lt;/P&gt;&lt;P&gt;Does write level support mean the DQ0 pin cannot be swapped? Or is the functionality supported on all pins.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;If memory device also matters, we plan to use: Micron&amp;nbsp;MT41K512M16&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;best regards,&lt;/P&gt;&lt;P&gt;Tom&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 13 Aug 2020 10:42:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1043A-DDR3L-data-bit-swap/m-p/1091339#M6445</guid>
      <dc:creator>tom_derks</dc:creator>
      <dc:date>2020-08-13T10:42:27Z</dc:date>
    </item>
    <item>
      <title>Re: LS1043A DDR3L data-bit swap</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1043A-DDR3L-data-bit-swap/m-p/1091340#M6446</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;It is possible to swap any bits within a byte lane. Please refer to the nxp appnote AN3940, Table 1. “DDR3 Designer Checklist”, No 45.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 14 Aug 2020 10:42:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1043A-DDR3L-data-bit-swap/m-p/1091340#M6446</guid>
      <dc:creator>r8070z</dc:creator>
      <dc:date>2020-08-14T10:42:43Z</dc:date>
    </item>
  </channel>
</rss>

