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    <title>topic PCIe loopback test in Layerscape</title>
    <link>https://community.nxp.com/t5/Layerscape/PCIe-loopback-test/m-p/1052827#M5976</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We are using LS1046A in our design. We have PCIe X2 lane and PCIe X1 lane both configured at Gen3. This is RC and the EP is Qualcomm device. I would like to run pcie loopback test between RC (LS1046A) and QCA device. to verify the overall throughput.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I got a sequence of commands that we have to execute to create a loopback from RC. I am able to confirm that loopback is created post reading the status. Now i would like to run pcie test. How to do that ??&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please suggest&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 20 Apr 2020 07:32:48 GMT</pubDate>
    <dc:creator>srinivas_hk</dc:creator>
    <dc:date>2020-04-20T07:32:48Z</dc:date>
    <item>
      <title>PCIe loopback test</title>
      <link>https://community.nxp.com/t5/Layerscape/PCIe-loopback-test/m-p/1052827#M5976</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We are using LS1046A in our design. We have PCIe X2 lane and PCIe X1 lane both configured at Gen3. This is RC and the EP is Qualcomm device. I would like to run pcie loopback test between RC (LS1046A) and QCA device. to verify the overall throughput.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I got a sequence of commands that we have to execute to create a loopback from RC. I am able to confirm that loopback is created post reading the status. Now i would like to run pcie test. How to do that ??&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please suggest&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 20 Apr 2020 07:32:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/PCIe-loopback-test/m-p/1052827#M5976</guid>
      <dc:creator>srinivas_hk</dc:creator>
      <dc:date>2020-04-20T07:32:48Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe loopback test</title>
      <link>https://community.nxp.com/t5/Layerscape/PCIe-loopback-test/m-p/1052828#M5977</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;You wrote:&lt;/P&gt;&lt;P&gt;&amp;gt; Now i would like to run pcie test.&lt;/P&gt;&lt;P&gt;Which exactly test you want to run?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 21 Apr 2020 16:05:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/PCIe-loopback-test/m-p/1052828#M5977</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2020-04-21T16:05:00Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe loopback test</title>
      <link>https://community.nxp.com/t5/Layerscape/PCIe-loopback-test/m-p/1052829#M5978</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Basically read write stress test between RC and EP. It can be a prbs pattern or some pattern which gets transmitted from RC&amp;nbsp; and when received it should match.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 22 Apr 2020 05:17:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/PCIe-loopback-test/m-p/1052829#M5978</guid>
      <dc:creator>srinivas_hk</dc:creator>
      <dc:date>2020-04-22T05:17:30Z</dc:date>
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