<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>LayerscapeのトピックRe: VTT termination with a single DDR4?</title>
    <link>https://community.nxp.com/t5/Layerscape/VTT-termination-with-a-single-DDR4/m-p/1004698#M5302</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Does it mean I need at least 2X DDR4 16 bit like the&amp;nbsp;MT40A512M16?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 25 Feb 2020 08:33:25 GMT</pubDate>
    <dc:creator>maxime_guillot</dc:creator>
    <dc:date>2020-02-25T08:33:25Z</dc:date>
    <item>
      <title>VTT termination with a single DDR4?</title>
      <link>https://community.nxp.com/t5/Layerscape/VTT-termination-with-a-single-DDR4/m-p/1004696#M5300</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am using the LS1046A for a new design with one DDR4 16 bits memory. In all the AN I read, there is mention of use of VTT termination resistors. Is it really mandatory even with only one DDR4 16 bits memory?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 24 Feb 2020 13:41:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/VTT-termination-with-a-single-DDR4/m-p/1004696#M5300</guid>
      <dc:creator>maxime_guillot</dc:creator>
      <dc:date>2020-02-24T13:41:22Z</dc:date>
    </item>
    <item>
      <title>Re: VTT termination with a single DDR4?</title>
      <link>https://community.nxp.com/t5/Layerscape/VTT-termination-with-a-single-DDR4/m-p/1004697#M5301</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;You wrote:&lt;/P&gt;&lt;P&gt;&amp;gt;&amp;nbsp;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;one DDR4 16 bits memory.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;The processor supports&amp;nbsp;data bus widths:&lt;BR /&gt;• 64-/72-bit&lt;BR /&gt;• 32-/40-bit&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Termination generally is required to match signals lines to eliminate excessive ringing.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 24 Feb 2020 17:20:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/VTT-termination-with-a-single-DDR4/m-p/1004697#M5301</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2020-02-24T17:20:38Z</dc:date>
    </item>
    <item>
      <title>Re: VTT termination with a single DDR4?</title>
      <link>https://community.nxp.com/t5/Layerscape/VTT-termination-with-a-single-DDR4/m-p/1004698#M5302</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Does it mean I need at least 2X DDR4 16 bit like the&amp;nbsp;MT40A512M16?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 25 Feb 2020 08:33:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/VTT-termination-with-a-single-DDR4/m-p/1004698#M5302</guid>
      <dc:creator>maxime_guillot</dc:creator>
      <dc:date>2020-02-25T08:33:25Z</dc:date>
    </item>
    <item>
      <title>Re: VTT termination with a single DDR4?</title>
      <link>https://community.nxp.com/t5/Layerscape/VTT-termination-with-a-single-DDR4/m-p/1004699#M5303</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 25 Feb 2020 08:51:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/VTT-termination-with-a-single-DDR4/m-p/1004699#M5303</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2020-02-25T08:51:15Z</dc:date>
    </item>
  </channel>
</rss>

