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    <title>LayerscapeのトピックLS1043A write enable signal in Async NAND Flash mode</title>
    <link>https://community.nxp.com/t5/Layerscape/LS1043A-write-enable-signal-in-Async-NAND-Flash-mode/m-p/998708#M5231</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I'm working with the LS1043A device and trying to figure out which write enable signal it will drive in Async NAND Flash mode.&amp;nbsp; In referring to the LS1043A Reference Manual (Rev. 4, 6/2018) Table 25-1 indicates that in Async NAND Flash mode IFC_NDDDR_CLK is driven as write enable NDWE_B.&amp;nbsp; Table 25-2 seems to agree with this in saying that IFC_NDDDR_CLK/NDWE_B is used as a write enable in Async NAND Flash mode and that WE[0]_B is used as a write enable in NOR/GPCM modes and as a SOF in GASIC mode.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;However, Figure 25-6 shows the WE0/SOF_L output from the IFC connecting to the NAND Flash write enable signal (WE_B) instead of IFC_NDDDR_CLK/NDWE_B which seems to disagree with the info listed in Tables 25-1 and 25-2.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In Async NAND Flash mode will the IFC drive the IFC_NDDDR_CLK/NDWE_B output as the write enable to the Flash or will it drive WE[0]_B output?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 24 Jan 2020 15:16:02 GMT</pubDate>
    <dc:creator>michael_machesk</dc:creator>
    <dc:date>2020-01-24T15:16:02Z</dc:date>
    <item>
      <title>LS1043A write enable signal in Async NAND Flash mode</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1043A-write-enable-signal-in-Async-NAND-Flash-mode/m-p/998708#M5231</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I'm working with the LS1043A device and trying to figure out which write enable signal it will drive in Async NAND Flash mode.&amp;nbsp; In referring to the LS1043A Reference Manual (Rev. 4, 6/2018) Table 25-1 indicates that in Async NAND Flash mode IFC_NDDDR_CLK is driven as write enable NDWE_B.&amp;nbsp; Table 25-2 seems to agree with this in saying that IFC_NDDDR_CLK/NDWE_B is used as a write enable in Async NAND Flash mode and that WE[0]_B is used as a write enable in NOR/GPCM modes and as a SOF in GASIC mode.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;However, Figure 25-6 shows the WE0/SOF_L output from the IFC connecting to the NAND Flash write enable signal (WE_B) instead of IFC_NDDDR_CLK/NDWE_B which seems to disagree with the info listed in Tables 25-1 and 25-2.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In Async NAND Flash mode will the IFC drive the IFC_NDDDR_CLK/NDWE_B output as the write enable to the Flash or will it drive WE[0]_B output?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 24 Jan 2020 15:16:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1043A-write-enable-signal-in-Async-NAND-Flash-mode/m-p/998708#M5231</guid>
      <dc:creator>michael_machesk</dc:creator>
      <dc:date>2020-01-24T15:16:02Z</dc:date>
    </item>
    <item>
      <title>Re: LS1043A write enable signal in Async NAND Flash mode</title>
      <link>https://community.nxp.com/t5/Layerscape/LS1043A-write-enable-signal-in-Async-NAND-Flash-mode/m-p/998709#M5232</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;It is a typo in our documentation in tables 25-1 and 25-2, IFC_WE0 signal is not well described. Actually either IFC_NDDDR_CLK or IFC_WE0 can be used as a Write Enable for async NAND flash. On our development boards we use IFC_WE0 as NAND's WE, it works fine.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Bulat&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 24 Jan 2020 16:32:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/LS1043A-write-enable-signal-in-Async-NAND-Flash-mode/m-p/998709#M5232</guid>
      <dc:creator>Bulat</dc:creator>
      <dc:date>2020-01-24T16:32:43Z</dc:date>
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