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    <title>Layerscape中的主题 Re: TFA on LS1012A noSEC</title>
    <link>https://community.nxp.com/t5/Layerscape/TFA-on-LS1012A-noSEC/m-p/985203#M5026</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello &lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Eivind&lt;/SPAN&gt;,&lt;/P&gt;&lt;P&gt;There should be no relation with the SEC module.&lt;/P&gt;&lt;P&gt;Would you please try whether BL31 can start up when copying BL31 to OCRAM rather than DDR DRAM?&lt;/P&gt;&lt;P&gt;For example, modify BL31 base address as the following in plat/nxp/soc-ls1012/ls1012ardb/platform_def.h.&lt;/P&gt;&lt;P&gt;#define BL2_BASE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; NXP_OCRAM_ADDR&lt;BR /&gt;#define BL2_LIMIT&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE/2)&lt;BR /&gt;#define BL2_TEXT_LIMIT&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (BL2_LIMIT - NXP_ROM_RSVD - CSF_HDR_SZ)&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;#define BL31_BASE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; NXP_OCRAM_ADDR + NXP_OCRAM_SIZE/2&lt;BR /&gt;#define BL31_SIZE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (0x200000)&lt;BR /&gt;#define BL31_LIMIT&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (BL31_BASE + BL31_SIZE)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Yiping&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 09 Jan 2020 09:38:27 GMT</pubDate>
    <dc:creator>yipingwang</dc:creator>
    <dc:date>2020-01-09T09:38:27Z</dc:date>
    <item>
      <title>TFA on LS1012A noSEC</title>
      <link>https://community.nxp.com/t5/Layerscape/TFA-on-LS1012A-noSEC/m-p/985200#M5023</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;We have a design with&amp;nbsp; &lt;SPAN class=""&gt;LS1012ASN7HKA-800MHz (NoSEC)&lt;/SPAN&gt;&amp;nbsp; that works very well with the PPA in earlier LSDK releases. When trying to get LSDK 1909 running on this board, the boot loader stalls at BL2 when trying to load BL31. We added some additional debug output and see that BL31 is never started. The build works very well on the LS1012ardb we based our design on. How do we get the TF-A to load u-boot?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Eivind&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 08 Jan 2020 15:06:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/TFA-on-LS1012A-noSEC/m-p/985200#M5023</guid>
      <dc:creator>dolphin1</dc:creator>
      <dc:date>2020-01-08T15:06:12Z</dc:date>
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    <item>
      <title>Re: TFA on LS1012A noSEC</title>
      <link>https://community.nxp.com/t5/Layerscape/TFA-on-LS1012A-noSEC/m-p/985201#M5024</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Eivind,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In the TFA boot flow, DDR initialization is not required in U-Boot. DDR initialization is a part of TFA.&lt;/P&gt;&lt;P&gt;DDR init code can be added to &amp;lt;atf_dir&amp;gt;/plat/nxp/soc-&amp;lt;soc-name&amp;gt;/&amp;lt;soc-name&amp;gt;ardb/ddr_init.c.&lt;/P&gt;&lt;P&gt;Please customize the following configuration for your custom board in packages/firmware/atf/plat/nxp/soc-ls1012/ls1012ardb/ddr_init.c.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; static const struct fsl_mmdc_info mparam = {&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; .mdctl = 0x05180000,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; .mdpdc = 0x00030035,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; .mdotc = 0x12554000,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; .mdcfg0 = 0xbabf7954,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; .mdcfg1 = 0xdb328f64,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; .mdcfg2 = 0x01ff00db,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; .mdmisc = 0x00001680,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; .mdref = 0x0f3c8000,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; .mdrwd = 0x00002000,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; .mdor = 0x00bf1023,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; .mdasp = 0x0000003f,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; .mpodtctrl = 0x0000022a,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; .mpzqhwctrl = 0xa1390003,&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; };&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In atf/plat/nxp/soc-ls1012/ls1012ardb/platform_def.h&lt;/P&gt;&lt;P&gt;define DDRC_NUM_CS&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 1&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /* use 1 chip-select */&lt;/P&gt;&lt;P&gt;#define PLAT_DEF_DRAM0_SIZE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x40000000&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; /*&amp;nbsp; 1G */&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please customize RCW file in packages/firmware/rcw/ls1012ardb/R_SPNH_3508/ for you custom board.&lt;/P&gt;&lt;P&gt;Then regenerate ATF images.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Yiping&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 09 Jan 2020 06:20:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/TFA-on-LS1012A-noSEC/m-p/985201#M5024</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2020-01-09T06:20:13Z</dc:date>
    </item>
    <item>
      <title>Re: TFA on LS1012A noSEC</title>
      <link>https://community.nxp.com/t5/Layerscape/TFA-on-LS1012A-noSEC/m-p/985202#M5025</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Hi Yiping,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;We already did that - same mmdc struct in atf as we had in u-boot (&lt;SPAN&gt;&amp;nbsp;.mdctl = 0x04180000,&amp;nbsp;&lt;SPAN style="background-color: #ffffff;"&gt;PLAT_DEF_DRAM0_SIZE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0x20000000)&lt;/SPAN&gt;&lt;/SPAN&gt;.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;The RCW is the same as before, and very similar to the RDB RCW.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Could the problem be related to the fact thas this chip is not SEC enabled, and that initialisation of SEC features happens in BL31?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Eivind&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 09 Jan 2020 07:47:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/TFA-on-LS1012A-noSEC/m-p/985202#M5025</guid>
      <dc:creator>dolphin1</dc:creator>
      <dc:date>2020-01-09T07:47:26Z</dc:date>
    </item>
    <item>
      <title>Re: TFA on LS1012A noSEC</title>
      <link>https://community.nxp.com/t5/Layerscape/TFA-on-LS1012A-noSEC/m-p/985203#M5026</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello &lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Eivind&lt;/SPAN&gt;,&lt;/P&gt;&lt;P&gt;There should be no relation with the SEC module.&lt;/P&gt;&lt;P&gt;Would you please try whether BL31 can start up when copying BL31 to OCRAM rather than DDR DRAM?&lt;/P&gt;&lt;P&gt;For example, modify BL31 base address as the following in plat/nxp/soc-ls1012/ls1012ardb/platform_def.h.&lt;/P&gt;&lt;P&gt;#define BL2_BASE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; NXP_OCRAM_ADDR&lt;BR /&gt;#define BL2_LIMIT&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE/2)&lt;BR /&gt;#define BL2_TEXT_LIMIT&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (BL2_LIMIT - NXP_ROM_RSVD - CSF_HDR_SZ)&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;#define BL31_BASE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; NXP_OCRAM_ADDR + NXP_OCRAM_SIZE/2&lt;BR /&gt;#define BL31_SIZE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (0x200000)&lt;BR /&gt;#define BL31_LIMIT&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; (BL31_BASE + BL31_SIZE)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Yiping&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 09 Jan 2020 09:38:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/TFA-on-LS1012A-noSEC/m-p/985203#M5026</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2020-01-09T09:38:27Z</dc:date>
    </item>
    <item>
      <title>Re: TFA on LS1012A noSEC</title>
      <link>https://community.nxp.com/t5/Layerscape/TFA-on-LS1012A-noSEC/m-p/985204#M5027</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Yiping,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;There's no space in OCRAM1+&lt;SPAN&gt;OCRAM2&lt;/SPAN&gt;&amp;nbsp;(64K + 64K) for BL2 and BL31&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;By the way: Where is TEST_BL31 defined?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Eivind&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 10 Jan 2020 11:21:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/TFA-on-LS1012A-noSEC/m-p/985204#M5027</guid>
      <dc:creator>dolphin1</dc:creator>
      <dc:date>2020-01-10T11:21:55Z</dc:date>
    </item>
    <item>
      <title>Re: TFA on LS1012A noSEC</title>
      <link>https://community.nxp.com/t5/Layerscape/TFA-on-LS1012A-noSEC/m-p/985205#M5028</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello Eivind,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please define TEST_BL31 as 1 in atf/plat/nxp/soc-ls1012/ls1012ardb/platform_def.h.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In addition, you could use CodeWarrior to verify whether DDR memory works normally.&lt;/P&gt;&lt;P&gt;You could connect CodeWarrior to the target board with CodeWarrior TAP or configuring the target board as CMSIS DAP mode.&lt;/P&gt;&lt;P&gt;Please create a bareboard project and check whether the sample program can run successfully in DDR memory.&lt;/P&gt;&lt;P&gt;Please refer to C:\Freescale\CW4NET_v2019.01\CW_ARMv8\ARMv8\Help\Getting_Started_for_CW_ARMv8.pdf.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Yiping&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 14 Jan 2020 02:59:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/TFA-on-LS1012A-noSEC/m-p/985205#M5028</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2020-01-14T02:59:22Z</dc:date>
    </item>
    <item>
      <title>Re: TFA on LS1012A noSEC</title>
      <link>https://community.nxp.com/t5/Layerscape/TFA-on-LS1012A-noSEC/m-p/985206#M5029</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I have a very similar problem with ls1043a and custom board.&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Boot log as follow:&lt;/P&gt;&lt;P&gt;INFO: RCW BOOT SRC is QSPI&lt;BR /&gt;INFO: RCW BOOT SRC is QSPI&lt;BR /&gt;INFO: Time before programming controller 0 ms&lt;/P&gt;&lt;P&gt;NOTICE: 2 GB DDR?, 32-bit, CL=11, ECC off&lt;BR /&gt;INFO: Time used by DDR driver 11 ms&lt;BR /&gt;NOTICE: BL2: v1.5(release):LSDK-19.09-dirty&lt;BR /&gt;NOTICE: BL2: Built : 17:17:21, Jan 14 2020&lt;BR /&gt;INFO: Configuring TZASC-380&lt;BR /&gt;INFO: BL2: Doing platform setup&lt;BR /&gt;INFO: BL2: Loading image id 3&lt;BR /&gt;INFO: Loading image id=3 at address 0xfbe00000&lt;BR /&gt;INFO: Image id=3 loaded: 0xfbe00000 - 0xfbe0b631&lt;BR /&gt;INFO: BL2: Loading image id 5&lt;BR /&gt;INFO: Loading image id=5 at address 0x82000000&lt;BR /&gt;INFO: Image id=5 loaded: 0x82000000 - 0x820b060b&lt;BR /&gt;NOTICE: BL2: Booting BL31&lt;BR /&gt;INFO: Entry point address = 0xfbe00000&lt;BR /&gt;INFO: SPSR = 0x3cd&amp;nbsp; &amp;nbsp;--­&amp;gt;&amp;nbsp; HANG...&lt;/P&gt;&lt;P&gt;DDR looks ok with QCVS.&amp;nbsp; We'll run tests with larger test area just in case...&lt;/P&gt;&lt;P&gt;I will also try to test with&amp;nbsp;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;TEST_BL31 and let you know.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Anyway, if you find the root cause, please keep us posted.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;Regards.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jan 2020 04:02:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/TFA-on-LS1012A-noSEC/m-p/985206#M5029</guid>
      <dc:creator>frank_o</dc:creator>
      <dc:date>2020-01-15T04:02:12Z</dc:date>
    </item>
    <item>
      <title>Re: TFA on LS1012A noSEC</title>
      <link>https://community.nxp.com/t5/Layerscape/TFA-on-LS1012A-noSEC/m-p/985207#M5030</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;You might have solve your problem already.&amp;nbsp; If not, this is what worked for me. One of the early u-boot init function was not crashing and because they execute before the console port is initialized, I was getting no output.&lt;/P&gt;&lt;P&gt;I did set a breakpoint in function "static inline int initcall_run_list()" in file u-boot/include/initcall.h and was able to find the&amp;nbsp;problem.&lt;/P&gt;&lt;P&gt;You can look at this other post for some&amp;nbsp;"missing link" about how to debug u-boot in CW.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/522216"&gt;JTAG load and execute u-boot on LS1043a and CodeWarrior with custom RCW/DRAM init&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Frank&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 02 Feb 2020 02:36:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/TFA-on-LS1012A-noSEC/m-p/985207#M5030</guid>
      <dc:creator>frank_o</dc:creator>
      <dc:date>2020-02-02T02:36:54Z</dc:date>
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