https://community.nxp.com/t5/Layerscape/Port-pin-status-during-RESET/m-p/984930#M5022 <HTML><HEAD></HEAD><BODY><P>The pin is tri-stated&nbsp;when PORESET_B is asserted.</P></BODY></HTML> Wed, 13 Nov 2019 17:51:43 GMT ufedor 2019-11-13T17:51:43Z https://community.nxp.com/t5/Layerscape/Port-pin-status-during-RESET/m-p/984929#M5021 <HTML><HEAD></HEAD><BODY><P>What is the port pin status of ball E13&nbsp;"IFC_PAR1/GPIO2_14/QSPI_DIO_B1/FTM6_CH1", while LS1021A is set into RESET state?</P><P>Datasheet (Rev. 7, 06/2019) doesn't&nbsp;provide any notes for this pin. Is there any internal weak pull resistor applied or is the pin in high-z mode?</P></BODY></HTML> Wed, 13 Nov 2019 07:44:10 GMT https://community.nxp.com/t5/Layerscape/Port-pin-status-during-RESET/m-p/984929#M5021 FK 2019-11-13T07:44:10Z https://community.nxp.com/t5/Layerscape/Port-pin-status-during-RESET/m-p/984930#M5022 <HTML><HEAD></HEAD><BODY><P>The pin is tri-stated&nbsp;when PORESET_B is asserted.</P></BODY></HTML> Wed, 13 Nov 2019 17:51:43 GMT https://community.nxp.com/t5/Layerscape/Port-pin-status-during-RESET/m-p/984930#M5022 ufedor 2019-11-13T17:51:43Z