Layerscape中的主题 BGA breakout routing dimensions, LS1046

BGA breakout routing dimensions, LS1046

dale_blankenshi — Thu, 03 Oct 2019 15:47:18 GMT

I am running pre-layout signal integrity simulations on the LS1046A PCIe lanes, and was looking for guidance on BGA breakout routing dimensions (worst-case) to use in HyperLynx. I'm currently assuming 6 mil trace width and 4 mil space, with a max length of 700 mils on the surface before the DC blocking capacitor (on the transmit side) and to a via to an internal layer. I don't know if I should assume a narrower trace width due to the BGA congestion.

Thanks.

Re: BGA breakout routing dimensions, LS1046

ufedor — Thu, 03 Oct 2019 16:55:31 GMT

It is possible to refer to the LS1046ARDB-PB layout which is included into the Design Files package available for download from:

QorIQ® LS1046A Development Board | NXP

Re: BGA breakout routing dimensions, LS1046

dale_blankenshi — Thu, 03 Oct 2019 17:05:14 GMT

Yes, thank you. That is essentially what I needed.