LayerscapeのトピックRe: Layerscape DDR4 PCB design https://community.nxp.com/t5/Layerscape/Layerscape-DDR4-PCB-design/m-p/938572#M4585 <HTML><HEAD></HEAD><BODY><P>Your understanding is correct.</P></BODY></HTML> Fri, 18 Oct 2019 19:00:01 GMT ufedor 2019-10-18T19:00:01Z Layerscape DDR4 PCB design https://community.nxp.com/t5/Layerscape/Layerscape-DDR4-PCB-design/m-p/938571#M4584 <HTML><HEAD></HEAD><BODY><P>Hello.</P><P>What&nbsp;does mean note in AN5097: "The clock signal trace from the memory controller to any given DDR4 chip should be longer than it's corresponding strobe trace lenghth"? Do I correct understood it's mean the CK signal must arrive from processor pins to corresponding DDR4 chip pins slightly later&nbsp;than corresponding DQS signal and CK trace lengths from processor to each memory chip must be longer than each corresponding DQS?</P></BODY></HTML> Fri, 18 Oct 2019 11:55:10 GMT https://community.nxp.com/t5/Layerscape/Layerscape-DDR4-PCB-design/m-p/938571#M4584 miha_at_work 2019-10-18T11:55:10Z Re: Layerscape DDR4 PCB design https://community.nxp.com/t5/Layerscape/Layerscape-DDR4-PCB-design/m-p/938572#M4585 <HTML><HEAD></HEAD><BODY><P>Your understanding is correct.</P></BODY></HTML> Fri, 18 Oct 2019 19:00:01 GMT https://community.nxp.com/t5/Layerscape/Layerscape-DDR4-PCB-design/m-p/938572#M4585 ufedor 2019-10-18T19:00:01Z