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    <title>topic Ls1046 abnormal crash in Layerscape</title>
    <link>https://community.nxp.com/t5/Layerscape/Ls1046-abnormal-crash/m-p/935706#M4516</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;Hi, I meet a problem: I desigend a board with ls1046(1.2GHz), reffer to ls1046rdb.&amp;nbsp; A simple boot which print i++, runs and abnormally crash with&amp;nbsp;&lt;SPAN class="" style="color: #333333; background-color: #f9f9f9;"&gt;no&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class="" style="color: #333333; background-color: #f9f9f9;"&gt;time regularity&lt;/SPAN&gt;, maybe crash in a few seconds or in &lt;SPAN style="color: #ab9d96; background-color: #f9f9f9;"&gt;a few minutes or one hour.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d;"&gt;&amp;nbsp; &amp;nbsp;I have measured the power supply &amp;amp; clk , nothing&amp;nbsp;abnormal found.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d;"&gt;&amp;nbsp; &amp;nbsp;I found that, the signal "hreset" may drop down a short time, "hreset" I use as input signal,4.7K res pull up, that means I do not drive on the signal . I also found "ifc_clk" change from 50MHz to 12.5MHz,&amp;nbsp; when Ls1046&amp;nbsp; crash., If not crash ,it will be always 50MHz. So, it seems LS1046'PLL crash.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d;"&gt;&amp;nbsp; &amp;nbsp; One mistake is that, I used 1.0v to power the vdd, when I check the datasheet, it should be 0.9v(1.2Ghz), will this destroy the IC? I have correct the vdd to 0.9v, but I cannot find anything abnormal in these days.&amp;nbsp; may somebody help me ?&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d;"&gt;&amp;nbsp; Thanks a lot.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d;"&gt;&amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 19 Aug 2019 09:32:21 GMT</pubDate>
    <dc:creator>411243223</dc:creator>
    <dc:date>2019-08-19T09:32:21Z</dc:date>
    <item>
      <title>Ls1046 abnormal crash</title>
      <link>https://community.nxp.com/t5/Layerscape/Ls1046-abnormal-crash/m-p/935706#M4516</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;Hi, I meet a problem: I desigend a board with ls1046(1.2GHz), reffer to ls1046rdb.&amp;nbsp; A simple boot which print i++, runs and abnormally crash with&amp;nbsp;&lt;SPAN class="" style="color: #333333; background-color: #f9f9f9;"&gt;no&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class="" style="color: #333333; background-color: #f9f9f9;"&gt;time regularity&lt;/SPAN&gt;, maybe crash in a few seconds or in &lt;SPAN style="color: #ab9d96; background-color: #f9f9f9;"&gt;a few minutes or one hour.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d;"&gt;&amp;nbsp; &amp;nbsp;I have measured the power supply &amp;amp; clk , nothing&amp;nbsp;abnormal found.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d;"&gt;&amp;nbsp; &amp;nbsp;I found that, the signal "hreset" may drop down a short time, "hreset" I use as input signal,4.7K res pull up, that means I do not drive on the signal . I also found "ifc_clk" change from 50MHz to 12.5MHz,&amp;nbsp; when Ls1046&amp;nbsp; crash., If not crash ,it will be always 50MHz. So, it seems LS1046'PLL crash.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d;"&gt;&amp;nbsp; &amp;nbsp; One mistake is that, I used 1.0v to power the vdd, when I check the datasheet, it should be 0.9v(1.2Ghz), will this destroy the IC? I have correct the vdd to 0.9v, but I cannot find anything abnormal in these days.&amp;nbsp; may somebody help me ?&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d;"&gt;&amp;nbsp; Thanks a lot.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #3d3d3d;"&gt;&amp;nbsp; &amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 19 Aug 2019 09:32:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Ls1046-abnormal-crash/m-p/935706#M4516</guid>
      <dc:creator>411243223</dc:creator>
      <dc:date>2019-08-19T09:32:21Z</dc:date>
    </item>
    <item>
      <title>Re: Ls1046 abnormal crash</title>
      <link>https://community.nxp.com/t5/Layerscape/Ls1046-abnormal-crash/m-p/935707#M4517</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Problem is solved．&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;First, 1.0V vdd will not damage ls1046 of 1.2GHz version.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Second, on my board, the "poreset_B" signal is interfered by the board main power, which is DC_12V.&amp;nbsp; I found that, the higher Voltage　of&amp;nbsp; power(like 13V),&amp;nbsp; more possibly LS1046 crash.&amp;nbsp; And&amp;nbsp; when I&amp;nbsp; measured the&amp;nbsp;&lt;SPAN&gt;"poreset_B"&amp;nbsp;&lt;/SPAN&gt;signal , Ls1046 can run well.&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;So, I suggest&amp;nbsp;&lt;SPAN&gt;&amp;nbsp;"poreset_B" have ａresistance pullup and 22pF cap to ground,&amp;nbsp; that will be beneficial.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 22 Aug 2019 09:00:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Ls1046-abnormal-crash/m-p/935707#M4517</guid>
      <dc:creator>411243223</dc:creator>
      <dc:date>2019-08-22T09:00:46Z</dc:date>
    </item>
    <item>
      <title>Re: Ls1046 abnormal crash</title>
      <link>https://community.nxp.com/t5/Layerscape/Ls1046-abnormal-crash/m-p/935708#M4518</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I have thinking about why "poreset_b" be interfaced these days, And found the vdd power ltc3866 may have some problem . I designed the ltc3866 reffer to the demo, but much high overshoot (p2p 22v max)found on the "sw" pin, that will worsen　the board power supply dc-12v, and the the dc-12v interfaces the "poreset_b".&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I check the datasheet of ltc3866, and&amp;nbsp; want to ask why "sgnd"&amp;amp;"gnd" are not one net, but connect them by 0&lt;SPAN&gt;Ω&lt;/SPAN&gt;-res(on the bom ,there is no&amp;nbsp; this ０Ω unexpectedly )?&amp;nbsp; &amp;nbsp;Dose anybody have the same problem?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 27 Aug 2019 01:29:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Ls1046-abnormal-crash/m-p/935708#M4518</guid>
      <dc:creator>411243223</dc:creator>
      <dc:date>2019-08-27T01:29:46Z</dc:date>
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