topic Re: LS2088A Coustom Board in Layerscape

LS2088A Coustom Board

prashantsoni — Wed, 29 May 2019 10:48:25 GMT

Hi NXP team,

Can we remove the CPLD from the LS2088A-rdb design and all the reset and critical signal on which LS2088A boot depends, can be driven by mosfet logics.

Re: LS2088A Coustom Board

ufedor — Wed, 29 May 2019 15:02:00 GMT

Of course CPLD is not absolutely required for the LS2088A-based designs.

The LS2088ARDB design was implemented using CPLD just because that it was convenient for the board designer.

Other approaches also are possible considering that requirements of the processor's Data Sheet and Design Checklist are fulfilled.

Re: LS2088A Coustom Board

prashantsoni — Sat, 12 Oct 2019 07:49:17 GMT

Hi Ufedor,

we have bypassed the cpld, but at the time we are doing DDR SPD read from CW tap we are facing issue. Can you please let me know the reset sequence to be followed at this DDR SPD read from CW TAP operation.