LS1024A Power Requirements & Nand Flash max size interfacable

tilakmarupilla — Sat, 13 Jul 2019 17:14:10 GMT

Dear all,

I'm a newbie to processor's world. Kindly help me understanding the below stuff:

I want to use LS1024A for its Crypto, USB 3.0 & Nand flash interfacing support.

* Unlike other Processor/MCU's,.... LS1024A's Electrical characteristics were not given. (Since I want to make a device which will be USB bus powered (5v,500-1A) can use USB Y cable )

How can I know my estimated power consumption (when using above mentioned Crypto,USB 3.0 & Nand)/ do some power management (switch off one A9 core..etc) to make power consumption < 1A.

* Is there any limit to the size of the flash devices that can be interfaced using Nand flash controller or EBI of LS1024A ?
(PS: I want to interface a 128GB (Giga Byte) Nand flash IC )

Thanks in advance.

PavelChubakov‌ ufedor‌ yipingwang‌ alexander.yakovlev‌ r8070z‌ ebiz_ws_prod‌

Re: LS1024A Power Requirements & Nand Flash max size interfacable

ufedor — Thu, 18 Jul 2019 02:50:01 GMT

LS1024A power consumption is provided in the AN4959, QorIQ LS1024A Family Thermal Application Considerations.
There is no"NAND controller"as such within LS1024A. There is an expansion bus which is used to connect to the NAND device. The IO bus on NAND devices is 8 bits wide. Higher address bits than this are used for the NAND control signals. The bus signals are controlled by software to apply the command cycle, address cycle(s) and data cycle(s) to the NAND device. There is no hardware limitation because software can apply whatever signals it wants.
The software release for this device includes NAND drivers that handle accesses to NAND.

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LS1024A Power Requirements & Nand Flash max size interfacable

Re: LS1024A Power Requirements & Nand Flash max size interfacable