Ehernet interface not up

jagadiswar_rao — Thu, 04 Apr 2019 13:02:36 GMT

Hi Team

We are using custom LS2088A board in which, we are using F104S8A Ethernet PHY for QSGMII interface.

We are getting the following error:

getting below kernel logs.

libphy: Freescale XGMAC MDIO Bus: probed
mdio_bus 8b96000: Error while reading PHY16 reg at 2.2
mdio_bus 8b96000: Error while reading PHY16 reg at 3.3
mdio_bus 8b96000: MDIO device at address 16 is missing.

There is no Ethernet interface is created.

ifconfig -a
docker0: flags=4098<BROADCAST,MULTICAST> mtu 1500
        inet 172.17.0.1 netmask 255.255.0.0 broadcast 172.17.255.255
        ether 02:42:cd:a0:f6:7e txqueuelen 0 (Ethernet)
        RX packets 0 bytes 0 (0.0 B)
        RX errors 0 dropped 0 overruns 0 frame 0
        TX packets 0 bytes 0 (0.0 B)
        TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING> mtu 65536
        inet 127.0.0.1 netmask 255.0.0.0
        inet6 ::1 prefixlen 128 scopeid 0x10<host>
        loop txqueuelen 1000 (Local Loopback)
        RX packets 0 bytes 0 (0.0 B)
        RX errors 0 dropped 0 overruns 0 frame 0
        TX packets 0 bytes 0 (0.0 B)
        TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0

sit0: flags=128<NOARP> mtu 1480
        sit txqueuelen 1000 (IPv6-in-IPv4)
        RX packets 0 bytes 0 (0.0 B)
        RX errors 0 dropped 0 overruns 0 frame 0
        TX packets 0 bytes 0 (0.0 B)
        TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0

Re: Ehernet interface not up

bpe — Tue, 09 Apr 2019 17:44:08 GMT

The kernel informs you that it is unable read certain registers in
the PHY and/or the PHY stops responding while being initialized.
This can be a Device Tree or a hardware issue. Suggestions:

1. Make sure you properly specified the PHY connection to the processor
   MDIO and the PHY management addresses in the Device Tree. Take
   fsl-ls1088a-rdb.dts as a reference.

2. Monitor MDIO/MDC interface with a scope, make sure the signal shapes
   meet the requirements of the processor and the PHY Hardware
   Specifications.

Have a great day,
Platon

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Ehernet interface not up

Re: Ehernet interface not up