External SRAM-like Bus Performance Limit due to Internal Bus Latency

aivchenko — Wed, 20 Feb 2019 14:31:41 GMT

Does Layerscape architecture like LS1028A or LS1046A have the same limitations on the external parallel bus?

Re: External SRAM-like Bus Performance Limit due to Internal Bus Latency

Pavel — Thu, 21 Feb 2019 04:45:40 GMT

The IFC controller is used for connection to NOR or SRAM memory.

This IFC controller supports burst size up to 256 bytes.

Usually qDMA is used for data transfers from memory to memory.

Have a great day,
Pavel Chubakov

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topic External SRAM-like Bus Performance Limit due to Internal Bus Latency in Layerscape

External SRAM-like Bus Performance Limit due to Internal Bus Latency

Re: External SRAM-like Bus Performance Limit due to Internal Bus Latency