<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>LayerscapeのトピックRe: Sample code wanted for configuring p1010 L2SRAM as pure SRAM and executing program code from it?</title>
    <link>https://community.nxp.com/t5/Layerscape/Sample-code-wanted-for-configuring-p1010-L2SRAM-as-pure-SRAM-and/m-p/439285#M404</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Sam&lt;/P&gt;&lt;P&gt;I am not sure which spl.s you are referring to but if&lt;/P&gt;&lt;P&gt;you like you can find the spl code that does this&lt;/P&gt;&lt;P&gt;in mainline u-boot/arch/powerpc/cpu/mpc85xx/spl_minimal.c&lt;/P&gt;&lt;P&gt;Look at the section enabled with CONFIG_SYS_INIT_L2_ADDR.&lt;/P&gt;&lt;P&gt;Hope this helps&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Sinan Akman&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 08 Oct 2015 04:58:47 GMT</pubDate>
    <dc:creator>sinanakman</dc:creator>
    <dc:date>2015-10-08T04:58:47Z</dc:date>
    <item>
      <title>Sample code wanted for configuring p1010 L2SRAM as pure SRAM and executing program code from it?</title>
      <link>https://community.nxp.com/t5/Layerscape/Sample-code-wanted-for-configuring-p1010-L2SRAM-as-pure-SRAM-and/m-p/439281#M400</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Is there any sample code for configuring p1010 L2SRAM as pure SRAM and executing program code from it?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 06 Oct 2015 18:54:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Sample-code-wanted-for-configuring-p1010-L2SRAM-as-pure-SRAM-and/m-p/439281#M400</guid>
      <dc:creator>samedwards</dc:creator>
      <dc:date>2015-10-06T18:54:56Z</dc:date>
    </item>
    <item>
      <title>Re: Sample code wanted for configuring p1010 L2SRAM as pure SRAM and executing program code from it?</title>
      <link>https://community.nxp.com/t5/Layerscape/Sample-code-wanted-for-configuring-p1010-L2SRAM-as-pure-SRAM-and/m-p/439282#M401</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Not answered yet.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 07 Oct 2015 15:06:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Sample-code-wanted-for-configuring-p1010-L2SRAM-as-pure-SRAM-and/m-p/439282#M401</guid>
      <dc:creator>samedwards</dc:creator>
      <dc:date>2015-10-07T15:06:38Z</dc:date>
    </item>
    <item>
      <title>Re: Sample code wanted for configuring p1010 L2SRAM as pure SRAM and executing program code from it?</title>
      <link>https://community.nxp.com/t5/Layerscape/Sample-code-wanted-for-configuring-p1010-L2SRAM-as-pure-SRAM-and/m-p/439283#M402</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Sam&lt;/P&gt;&lt;P&gt;How are you intending to run the code for setting l2sram ?&lt;/P&gt;&lt;P&gt;I use a BDI3000 JTAG debugger and with it I can initialize&lt;/P&gt;&lt;P&gt;this as follows :&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;; Move the 256kB L2SRAM to the initial MMU page&lt;/P&gt;&lt;P&gt;WM32 0xFF720E44 0x0000001C ;L2ERRDIS: disable parity error&lt;/P&gt;&lt;P&gt;WM32 0xFF720000 0x50010000 ;L2CTL&lt;/P&gt;&lt;P&gt;WM32 0xFF720100 0xFFFC0000 ;L2SRBAR0: map to 0x0_FFFC0000&lt;/P&gt;&lt;P&gt;WM32 0xFF720104 0x00000000 ;L2SRBAREA0&lt;/P&gt;&lt;P&gt;WM32 0xFF720000 0x90010000 ;L2CTL&lt;/P&gt;&lt;P&gt;;&lt;/P&gt;&lt;P&gt;; load and execute some boot code&lt;/P&gt;&lt;P&gt;WM32 0xfffffffc 0x48000000 ;loop&lt;/P&gt;&lt;P&gt;EXEC 0xfffffffc&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Perhaps this gives you an idea and you can transform it&lt;/P&gt;&lt;P&gt;to your usage.&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Sinan Akman&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 07 Oct 2015 15:49:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Sample-code-wanted-for-configuring-p1010-L2SRAM-as-pure-SRAM-and/m-p/439283#M402</guid>
      <dc:creator>sinanakman</dc:creator>
      <dc:date>2015-10-07T15:49:09Z</dc:date>
    </item>
    <item>
      <title>Re: Sample code wanted for configuring p1010 L2SRAM as pure SRAM and executing program code from it?</title>
      <link>https://community.nxp.com/t5/Layerscape/Sample-code-wanted-for-configuring-p1010-L2SRAM-as-pure-SRAM-and/m-p/439284#M403</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Sinan,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for your reply. I intend to run the code in the spl.s program, in the section prior to where spl copies itself from NAND to RAM and continues execution. Presently it is written to copy itself to SDRAM, I want it to execute from SRAM instead. I will translate your sample to the equivalent syntax and report back the results.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Kind regards,&lt;/P&gt;&lt;P&gt;Sam&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 07 Oct 2015 22:00:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Sample-code-wanted-for-configuring-p1010-L2SRAM-as-pure-SRAM-and/m-p/439284#M403</guid>
      <dc:creator>samedwards</dc:creator>
      <dc:date>2015-10-07T22:00:39Z</dc:date>
    </item>
    <item>
      <title>Re: Sample code wanted for configuring p1010 L2SRAM as pure SRAM and executing program code from it?</title>
      <link>https://community.nxp.com/t5/Layerscape/Sample-code-wanted-for-configuring-p1010-L2SRAM-as-pure-SRAM-and/m-p/439285#M404</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Sam&lt;/P&gt;&lt;P&gt;I am not sure which spl.s you are referring to but if&lt;/P&gt;&lt;P&gt;you like you can find the spl code that does this&lt;/P&gt;&lt;P&gt;in mainline u-boot/arch/powerpc/cpu/mpc85xx/spl_minimal.c&lt;/P&gt;&lt;P&gt;Look at the section enabled with CONFIG_SYS_INIT_L2_ADDR.&lt;/P&gt;&lt;P&gt;Hope this helps&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Sinan Akman&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 08 Oct 2015 04:58:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Sample-code-wanted-for-configuring-p1010-L2SRAM-as-pure-SRAM-and/m-p/439285#M404</guid>
      <dc:creator>sinanakman</dc:creator>
      <dc:date>2015-10-08T04:58:47Z</dc:date>
    </item>
    <item>
      <title>Re: Sample code wanted for configuring p1010 L2SRAM as pure SRAM and executing program code from it?</title>
      <link>https://community.nxp.com/t5/Layerscape/Sample-code-wanted-for-configuring-p1010-L2SRAM-as-pure-SRAM-and/m-p/439286#M405</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Sinan,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for providing the spl_minimal.c code reference. My application uses VxWorks’ RTOS and the spl is part of the custom bsp provided by WindRiver.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best,&lt;/P&gt;&lt;P&gt;Sam&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 08 Oct 2015 13:29:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Sample-code-wanted-for-configuring-p1010-L2SRAM-as-pure-SRAM-and/m-p/439286#M405</guid>
      <dc:creator>samedwards</dc:creator>
      <dc:date>2015-10-08T13:29:56Z</dc:date>
    </item>
    <item>
      <title>Re: Sample code wanted for configuring p1010 L2SRAM as pure SRAM and executing program code from it?</title>
      <link>https://community.nxp.com/t5/Layerscape/Sample-code-wanted-for-configuring-p1010-L2SRAM-as-pure-SRAM-and/m-p/439287#M406</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Sam&lt;/P&gt;&lt;P&gt;OK so this is from VxWorks. The code should&lt;/P&gt;&lt;P&gt;work there as well, you just need to make sure&lt;/P&gt;&lt;P&gt;it lined up well with the address space it is setting&lt;/P&gt;&lt;P&gt;and that there is no clash for L2SRAM.&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;Sinan Akman&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 08 Oct 2015 18:07:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Sample-code-wanted-for-configuring-p1010-L2SRAM-as-pure-SRAM-and/m-p/439287#M406</guid>
      <dc:creator>sinanakman</dc:creator>
      <dc:date>2015-10-08T18:07:04Z</dc:date>
    </item>
  </channel>
</rss>

