topic Power on Sequence for LS2088A in Layerscape https://community.nxp.com/t5/Layerscape/Power-on-Sequence-for-LS2088A/m-p/863322#M3950 <HTML><HEAD></HEAD><BODY><P>Hi,</P><P>I am using LS2088A in a project.</P><P>Below is the power on sequencing which I am implementing in my circuit.&nbsp;</P><P>Initially all the IO and PLL power rails (3.3V, 1.8V, 1.35V, 1V_SVDD, 1V_USBSVDD) are released.</P><P>After all these power rails are released then the 1V05 core voltage is released and then the 1V2 DDR supply voltage is released.</P><P></P><P>Please let me know whether this sequence is fine or any correction is required.</P></BODY></HTML> Sat, 02 Mar 2019 14:33:50 GMT sekuru_saimukhe 2019-03-02T14:33:50Z Power on Sequence for LS2088A https://community.nxp.com/t5/Layerscape/Power-on-Sequence-for-LS2088A/m-p/863322#M3950 <HTML><HEAD></HEAD><BODY><P>Hi,</P><P>I am using LS2088A in a project.</P><P>Below is the power on sequencing which I am implementing in my circuit.&nbsp;</P><P>Initially all the IO and PLL power rails (3.3V, 1.8V, 1.35V, 1V_SVDD, 1V_USBSVDD) are released.</P><P>After all these power rails are released then the 1V05 core voltage is released and then the 1V2 DDR supply voltage is released.</P><P></P><P>Please let me know whether this sequence is fine or any correction is required.</P></BODY></HTML> Sat, 02 Mar 2019 14:33:50 GMT https://community.nxp.com/t5/Layerscape/Power-on-Sequence-for-LS2088A/m-p/863322#M3950 sekuru_saimukhe 2019-03-02T14:33:50Z Re: Power on Sequence for LS2088A https://community.nxp.com/t5/Layerscape/Power-on-Sequence-for-LS2088A/m-p/863323#M3951 <HTML><HEAD></HEAD><BODY><P>Described sequence is in accordance with the QorIQ LS2088A/LS2048A Data Sheet, 3.2 Power sequencing assuming that:</P><P>1) VDD is at 90% of its value before GnVDD reaches 10% of its value</P><P>2) All supply voltages are stable within 400 ms.</P></BODY></HTML> Mon, 04 Mar 2019 05:22:09 GMT https://community.nxp.com/t5/Layerscape/Power-on-Sequence-for-LS2088A/m-p/863323#M3951 ufedor 2019-03-04T05:22:09Z