LS1021A / LS1043A ARM Distributor Register

niharunadkat — Thu, 24 Jan 2019 22:59:25 GMT

I have written a kernel driver that reads the ARM distributor register for both LS1021a and LS1043a.

What i am trying to do is put my phase on a different cpu other then cpu0 of LS1043a.

NOTE: I know that the IRQ's for LS1021a and LS1043a are different.

Please see below

pgic = (unsigned char *) ioremap_nocache(0x01401000,0x00001000);

printk(KERN_ALERT "pgic[0x800 + 164] = %0x\n", pgic[0x800 + 164]);
printk(KERN_ALERT "pgic[0x400 + 164] = %0x\n", pgic[0x400 + 164]);
irq = irq_of_parse_and_map(np, 0);

ret = request_irq(irq, int27_phase_interrupt, irqflags, "phase", 0);

irq_set_affinity_hint(irq, get_cpu_mask(1));

When i insmod this driver in LS1021a i get the following output which works

pgic[0x800 + 164] = 1
pgic[0x400 + 164] = 10
pgic[0x800 + 164] = 2
pgic[0x400 + 164] = 10
Phase IRQ = 24

When i insmod the same driver on LS1043a I get the following output which does not work

pgic[0x800 + 164] = 0
pgic[0x400 + 164] = 0
pgic[0x800 + 164] = 0
pgic[0x400 + 164] = 0
Phase IRQ = 27

My question is that is the below register address correct to for LS1043a

pgic = (unsigned char *) ioremap_nocache(0x01401000,0x00001000);

If not than please let me know what the CCSR address Map should be. and if the offset is wrong please let me know that too.

And what would be the GICD_IPRIORITYRn and GICD_ITARGETSRn register address for LS1043a

Also i tried to read other address on the LS1043a with the above CCSR address Map, and this is what i got

pgic[0x008 + 0] = 0
pgic[0x008 + 1] = 0
pgic[0x008 + 2] = 0
pgic[0x008 + 3] = 0
pgic[0x008 + 4] = 0
pgic[0x008 + 5] = 0
pgic[0x008 + 6] = 0
pgic[0x008 + 7] = 0
pgic[0x008 + 8] = 0
pgic[0x008 + 9] = 0
pgic[0x008 + 10] = 0
pgic[0x008 + 11] = 0
pgic[0x008 + 12] = 0
pgic[0x008 + 13] = 0
pgic[0x008 + 14] = 0
pgic[0x008 + 15] = 0
pgic[0x008 + 16] = 0
pgic[0x008 + 17] = 0
pgic[0x008 + 18] = 0
pgic[0x008 + 19] = 0
pgic[0x008 + 20] = 0
pgic[0x008 + 21] = 0
pgic[0x008 + 22] = 0
pgic[0x008 + 23] = 0
pgic[0x008 + 24] = 0
pgic[0x008 + 25] = 0
pgic[0x008 + 26] = 0
pgic[0x008 + 27] = 0
pgic[0x008 + 28] = 0
pgic[0x008 + 29] = 0
pgic[0x008 + 30] = 0

It looks like I am reading the wrong CCSR address Map, but that's the address I found from the CoreLink GIC-400 Generic Interrupt Controller Revision:r0p0 manual. This is the link to that manual

http://docs-api-peg.northeurope.cloudapp.azure.com/assets/ihi0048/b/IHI0048B_b_gic_architecture_specification.pdf

Any help or advice would greatly be appreciated

Thank you

Nihar

Re: LS1021A / LS1043A ARM Distributor Register

ufedor — Mon, 28 Jan 2019 12:55:36 GMT

> pgic = (unsigned char *) ioremap_nocache(0x01401000,0x00001000);

The register supports only 32-bit access size.

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LS1021A / LS1043A ARM Distributor Register

Re: LS1021A / LS1043A ARM Distributor Register