LayerscapeのトピックRe: LS1043A CSn bus timing issue

LS1043A CSn bus timing issue

garybeck — Mon, 07 Jan 2019 22:20:35 GMT

We have a custom LS1043A board with the following peripherals mapped

CS0 - NOR Flash (256MB)

CS1 - NOR Flash (256MB)

CS2 - 8 bit GPCM (64KB)

CS3 - 16 bit GPCM (64KB)

Seeing some strange bus timing on CS2 and CS3 when CS0 write cycles are heavily utilized. Seems as though the write cycle timing from the CS0 region is being applied to the write cycles for the CS2&3 regions for a short period of time. The bus timing does revert back to the programmed values once the CS0 accesses cease. The bus timing for CS0 is the same as the RDB. The bus timing for CS2&3 are much longer (x10) due to design constraints.

Has anyone seen varying bus timing on the LS1043A IFC interface? Is there any errata?

Thanks

Re: LS1043A CSn bus timing issue

ufedor — Tue, 08 Jan 2019 02:59:08 GMT

Please note that RB signal function for GPCM is External Termination of Access.

Ensure that RB signal corresponding to the CS2&3 is not floating.

Re: LS1043A CSn bus timing issue

garybeck — Tue, 08 Jan 2019 16:19:39 GMT

Found the issue. In 28-bit addressing mode the RB0 input is used for the RB signal for all other CSn besides CS1. With heavy write accesses to both NOR flash (CS0) and FPGA (CS3), the FPGA accesses were terminating early due to RY/BY# signal from NOR flash.

CPLD design is largely copied from RDB design. The logic for the RB0 signal has been updated to be qualified with CS0.

Thanks for the help