topic Re: Manually Enabling QSPI Writes Through Mainline U-Boot in Layerscape

Manually Enabling QSPI Writes Through Mainline U-Boot

patrickmorrow — Wed, 25 Mar 2015 21:51:37 GMT

We are using the LS1021A-TWR Board.

We are running Mainline U-Boot 2015.01 off of an SD Card.

The following is our physical switch configuration and RCW:

SW2[1-8]: [OFF] [OFF] [ON] [OFF] [OFF] [ON] [ON] [OFF]

SW3[1-8]: [OFF] [ON] [ON] [OFF] [ON] [OFF] [OFF] [ON]

RCW:

0608000a 00000000 00000000 00000000

20000000 00407900 60025A00 21046000

00000000 00000000 00000000 21038000

20024800 881B1540 00000000 00000000

Issuing U-Boot "md" commands to addresses in the 0x0155XXXX CCSR QSPI and 0x4XXXXXXX QSPI address spaces appear to complete successfully in that they produce an output and do not hang.

In our most recent attempt at manually switching on QSPI Write Enable, we used the U-Boot "mm" command to write the following values to the corresponding addresses.

Address	Value	Intention
0x01550310	0x06041808	Queue the command (04) for "Write Enable" (06) where the bit length of the associated memory address (08) is 18h.
0x01550314	0x00000000	Declare that no additional data will be sent with the command (0000).
0x01550100	0x00000040	The previously mentioned 18h=24d bit address is 0x000000 (indicating that this command does not write to the QSPI storage).
0x01550008	0x00000000	Issue the command and write 0 bytes of return data to 0x01550200.
0x01550310	0x05041808	Queue another command (04) for "Read Status Register" (05) where the bit length of the associated memory address (08) is 18h.
0x01550314	0x011C0000	Declare a read (1C) of 01 byte then declare that no additional data will be sent with the command (0000).
0x01550100	0x00000040	The previously mentioned 18h=24d bit address is 0x000000 (indicating that this command does not write to the QSPI storage).
0x01550008	0x01000000	Issue the command and write 01 byte of return data to 0x01550200.

Each "mm" command has been verified as being successful through the use of the "md" command.

After the above commands, the write latch bit (bit #1) in the Status Register should be 1 as indicated by Micron's N25Q512A Serial NOR Flash Documentation but it is still 0.

To clarify, this question solely relates to QSPI and we are not experiencing any problems with U-Boot or booting Linux from an SD Card.

Any direction would be greatly appreciated. Thank you in advance!

Re: Manually Enabling QSPI Writes Through Mainline U-Boot

yipingwang — Thu, 26 Mar 2015 11:55:15 GMT

Hello Patrick Morrow,

Since IFC and QSPI/SPI are pin mutiplexed, in SDK 1.7 IFC isn't supported, and QSPI/SPI is supported in SD boot mode, for the mainline u-boot, there should be a patched applied to adjust the feature to support IFC instead. So now IFC is supported and QSPI is disabled.

So please try whether it would be helpful to make attached patch reverted to enable QSPI again.

For switch and RCW setting, please refer to this thread Re: LS1021A - QSPI Flash on ls1021atwr not found.

In addition, please use the following commands to do verification in u-boot.

=> sf probe 0:0

=> sf erase 0 100000

=> sf write 82000000 0 1000

=> sf read 81100000 0 1000

Have a great day,
Yiping

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Re: Manually Enabling QSPI Writes Through Mainline U-Boot

patrickmorrow — Fri, 27 Mar 2015 17:05:12 GMT

Applying the patch did not produce any changes within our current access of the QSPI flash from u-boot. Our attempts to access the QSPI may be skipping over a few important things that need to be fixed first. We may have jumped the gun when trying to ask about accessing the QSPI flash.