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    <title>Layerscape中的主题 Re: Where in the LS1012a-Freedom code is GPIO_RST_B controlled?</title>
    <link>https://community.nxp.com/t5/Layerscape/Where-in-the-LS1012a-Freedom-code-is-GPIO-RST-B-controlled/m-p/834823#M3769</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;It could be more convenient to create new question for the software debugging issue.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 30 Aug 2018 01:48:26 GMT</pubDate>
    <dc:creator>ufedor</dc:creator>
    <dc:date>2018-08-30T01:48:26Z</dc:date>
    <item>
      <title>Where in the LS1012a-Freedom code is GPIO_RST_B controlled?</title>
      <link>https://community.nxp.com/t5/Layerscape/Where-in-the-LS1012a-Freedom-code-is-GPIO-RST-B-controlled/m-p/834820#M3766</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Our custom board design diverged from the LS1012a Freedom reference board in that we have an eMMC on SDHC controller 1 and therefore need to configure pin 75 to SDHC1_VSEL (rather than GPIO1[23]). We moved this signal to pin 122 (GPIO1[13]).&lt;/P&gt;&lt;P&gt;&lt;EM&gt;Pin 122 is not connected to anything on the Freedom board. The LS1012A RM says the bit 424-425 RCW value of "11" is "GPIO1[13], RESET_REQ_B". We did not change RESET_REQ_B so I left this unchanged. &lt;STRONG&gt;Note:&lt;/STRONG&gt; the CodeWarrior IDE RCW configuration tool indicates that "11" is reserved (and not what it how it mux's these pins.&lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;However, I am unable to locate where in the code GPIO1[23] is utilized to reset the Ethernet PHYs and our PHYs appear to be held in reset.&lt;/P&gt;&lt;P&gt;Can anyone point me to the code I need to study/modify?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks!&lt;/P&gt;&lt;P&gt;.Tim&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 28 Aug 2018 20:10:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Where-in-the-LS1012a-Freedom-code-is-GPIO-RST-B-controlled/m-p/834820#M3766</guid>
      <dc:creator>timhammer</dc:creator>
      <dc:date>2018-08-28T20:10:22Z</dc:date>
    </item>
    <item>
      <title>Re: Where in the LS1012a-Freedom code is GPIO_RST_B controlled?</title>
      <link>https://community.nxp.com/t5/Layerscape/Where-in-the-LS1012a-Freedom-code-is-GPIO-RST-B-controlled/m-p/834821#M3767</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;A class="link-titled" href="https://github.com/qoriq-open-source/u-boot/blob/b3f98d438eefd1b355efdec0b50af5813ff8d0e1/board/freescale/ls1012afrx/eth.c" title="https://github.com/qoriq-open-source/u-boot/blob/b3f98d438eefd1b355efdec0b50af5813ff8d0e1/board/freescale/ls1012afrx/eth.c"&gt;u-boot/eth.c at b3f98d438eefd1b355efdec0b50af5813ff8d0e1 · qoriq-open-source/u-boot · GitHub&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;procedure "&lt;SPAN class=""&gt;ls1012afrdm_reset_phy"&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 29 Aug 2018 04:34:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Where-in-the-LS1012a-Freedom-code-is-GPIO-RST-B-controlled/m-p/834821#M3767</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2018-08-29T04:34:50Z</dc:date>
    </item>
    <item>
      <title>Re: Where in the LS1012a-Freedom code is GPIO_RST_B controlled?</title>
      <link>https://community.nxp.com/t5/Layerscape/Where-in-the-LS1012a-Freedom-code-is-GPIO-RST-B-controlled/m-p/834822#M3768</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/ufedor"&gt;ufedor&lt;/A&gt;‌ -&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for the pointer. I was able to modify the mask to use the correct GPIO line. That enabled one of the two PHYs. Where I was getting:&lt;/P&gt;&lt;P style="margin-left: .5in;"&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;Net: PFE class pe firmware&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-left: .5in;"&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;PFE tmu pe firmware&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-left: .5in;"&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;pfe_configure_serdes 0&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-left: .5in;"&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;Could not get PHY for PFE_MDIO: addr 2&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-left: .5in;"&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;phy_connect failed&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-left: .5in;"&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;pfe_configure_serdes 1&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-left: .5in;"&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;Could not get PHY for PFE_MDIO: addr 1&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-left: .5in;"&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;phy_connect failed&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-left: .5in;"&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;No ethernet found.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am now getting:&lt;/P&gt;&lt;P style="margin-left: .5in;"&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;Net: PFE class pe firmware&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-left: .5in;"&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;PFE tmu pe firmware&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-left: .5in;"&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;pfe_configure_serdes 0&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-left: .5in;"&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;pfe_configure_serdes 1&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-left: .5in;"&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;Could not get PHY for PFE_MDIO: addr 1&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-left: .5in;"&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;phy_connect failed&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-left: .5in;"&gt;&lt;SPAN style="font-size: 14.6667px;"&gt;pfe_eth0&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Similarly, in Linux the error has changed from:&lt;/P&gt;&lt;P style="margin-left: .5in;"&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;libphy: PHY ls1012a-0:02 not found&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-left: .5in;"&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;pfe 4000000.pfe eth0: phy_connect() failed&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-left: .5in;"&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;pfe 4000000.pfe eth0: pfe_eth_init_one: pfe_phy_init() failed&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;to:&lt;/P&gt;&lt;P style="margin-left: .5in;"&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;libphy: PHY ls1012a-0:01 not found&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-left: .5in;"&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;pfe 4000000.pfe eth1: phy_connect() failed&lt;/SPAN&gt;&lt;/P&gt;&lt;P style="margin-left: .5in;"&gt;&lt;SPAN style="font-size: 11.0pt;"&gt;pfe 4000000.pfe eth1: pfe_eth_init_one: pfe_phy_init() failed&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 29 Aug 2018 15:56:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Where-in-the-LS1012a-Freedom-code-is-GPIO-RST-B-controlled/m-p/834822#M3768</guid>
      <dc:creator>timhammer</dc:creator>
      <dc:date>2018-08-29T15:56:02Z</dc:date>
    </item>
    <item>
      <title>Re: Where in the LS1012a-Freedom code is GPIO_RST_B controlled?</title>
      <link>https://community.nxp.com/t5/Layerscape/Where-in-the-LS1012a-Freedom-code-is-GPIO-RST-B-controlled/m-p/834823#M3769</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;It could be more convenient to create new question for the software debugging issue.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 30 Aug 2018 01:48:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Where-in-the-LS1012a-Freedom-code-is-GPIO-RST-B-controlled/m-p/834823#M3769</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2018-08-30T01:48:26Z</dc:date>
    </item>
    <item>
      <title>Re: Where in the LS1012a-Freedom code is GPIO_RST_B controlled?</title>
      <link>https://community.nxp.com/t5/Layerscape/Where-in-the-LS1012a-Freedom-code-is-GPIO-RST-B-controlled/m-p/834824#M3770</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We subsequently identified an issue in the schematics that was causing one of the PHYs to have an incorrect address. We are now able to work with both Ethernet connections.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for following up.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 31 Aug 2018 18:34:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/Where-in-the-LS1012a-Freedom-code-is-GPIO-RST-B-controlled/m-p/834824#M3770</guid>
      <dc:creator>timhammer</dc:creator>
      <dc:date>2018-08-31T18:34:52Z</dc:date>
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