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    <title>topic Re: PCI-E Switch not normal working on LS1012A in Layerscape</title>
    <link>https://community.nxp.com/t5/Layerscape/PCI-E-Switch-not-normal-working-on-LS1012A/m-p/834754#M3765</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #2e3033; background-color: #eef0f2; font-weight: normal; font-size: 12px;"&gt;Have you solved your problem?&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 19 Mar 2019 03:20:24 GMT</pubDate>
    <dc:creator>zhangxiang1</dc:creator>
    <dc:date>2019-03-19T03:20:24Z</dc:date>
    <item>
      <title>PCI-E Switch not normal working on LS1012A</title>
      <link>https://community.nxp.com/t5/Layerscape/PCI-E-Switch-not-normal-working-on-LS1012A/m-p/834752#M3763</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;We added the PCI-E Switch(PI7C9X2G304SLBFDE) on our LS1012A dev board,&lt;BR /&gt; sometimes can't detected PCE-E Switch information after entering the file system,&lt;BR /&gt; Test ten times to boot, four times have the problems,&lt;BR /&gt; We debug&amp;nbsp;ls1012a pci-e drivers, ls_pcie_link_up function returned 0, because&amp;nbsp;&lt;SPAN style="font-size: 12.0pt;"&gt;state is&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN style="font-size: 12.0pt;"&gt;0xD &amp;lt; LTSSM_PCIE_L0,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="2.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/65972iAF965C84783C2E80/image-size/large?v=v2&amp;amp;px=999" role="button" title="2.png" alt="2.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt; How to fix this issue? &lt;BR /&gt; &lt;BR /&gt; LS1012A LSDK version: 1803&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Log:&lt;BR /&gt; u-boot PCI-E info:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="Image 2.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/65973i1B4DFE2FC088AD53/image-size/large?v=v2&amp;amp;px=999" role="button" title="Image 2.png" alt="Image 2.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;=====================================================&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;not detected:&lt;/P&gt;&lt;P&gt;root@localhost:~# lspci -vvv&lt;BR /&gt;00:00.0 PCI bridge: Freescale Semiconductor Inc Device 8101 (rev 10) (prog-if 00 [Normal decode])&lt;BR /&gt; Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-&lt;BR /&gt; Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast &amp;gt;TAbort- &amp;lt;TAbort- &amp;lt;MAbort- &amp;gt;SERR- &amp;lt;PERR- INTx-&lt;BR /&gt; Latency: 0, Cache Line Size: 32 bytes&lt;BR /&gt; Interrupt: pin A routed to IRQ 29&lt;BR /&gt; Bus: primary=00, secondary=01, subordinate=01, sec-latency=0&lt;BR /&gt; I/O behind bridge: 0000f000-00000fff&lt;BR /&gt; Memory behind bridge: fff00000-000fffff&lt;BR /&gt; Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff&lt;BR /&gt; Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast &amp;gt;TAbort- &amp;lt;TAbort- &amp;lt;MAbort+ &amp;lt;SERR- &amp;lt;PERR-&lt;BR /&gt; Expansion ROM at 4040000000 [disabled] [size=2K]&lt;BR /&gt; BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- &amp;gt;Reset- FastB2B-&lt;BR /&gt; PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-&lt;BR /&gt; Capabilities: [40] Power Management version 3&lt;BR /&gt; Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)&lt;BR /&gt; Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-&lt;BR /&gt; Capabilities: [50] MSI: Enable- Count=1/16 Maskable- 64bit+&lt;BR /&gt; Address: 0000000000000000 Data: 0000&lt;BR /&gt; Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00&lt;BR /&gt; DevCap: MaxPayload 256 bytes, PhantFunc 0&lt;BR /&gt; ExtTag- RBE+&lt;BR /&gt; DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+&lt;BR /&gt; RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+&lt;BR /&gt; MaxPayload 128 bytes, MaxReadReq 512 bytes&lt;BR /&gt; DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-&lt;BR /&gt; LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L0s, Exit Latency L0s unlimited, L1 unlimited&lt;BR /&gt; ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+&lt;BR /&gt; LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- CommClk-&lt;BR /&gt; ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-&lt;BR /&gt; LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt+ ABWMgmt+&lt;BR /&gt; RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible-&lt;BR /&gt; RootCap: CRSVisible-&lt;BR /&gt; RootSta: PME ReqID 0000, PMEStatus- PMEPending-&lt;BR /&gt; DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd-&lt;BR /&gt; DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-&lt;BR /&gt; LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-&lt;BR /&gt; Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-&lt;BR /&gt; Compliance De-emphasis: -6dB&lt;BR /&gt; LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1-&lt;BR /&gt; EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-&lt;BR /&gt; Capabilities: [100 v2] Advanced Error Reporting&lt;BR /&gt; UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-&lt;BR /&gt; UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-&lt;BR /&gt; UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-&lt;BR /&gt; CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-&lt;BR /&gt; CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+&lt;BR /&gt; AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-&lt;BR /&gt; Capabilities: [148 v1] #19&lt;BR /&gt; Kernel driver in use: pcieport&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;=====================================================&lt;/P&gt;&lt;P&gt;can detected:&lt;/P&gt;&lt;P&gt;root@localhost:~# lspci -vvv&lt;BR /&gt;00:00.0 PCI bridge: Freescale Semiconductor Inc Device 8101 (rev 10) (prog-if 00 [Normal decode])&lt;BR /&gt; Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-&lt;BR /&gt; Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast &amp;gt;TAbort- &amp;lt;TAbort- &amp;lt;MAbort- &amp;gt;SERR- &amp;lt;PERR- INTx-&lt;BR /&gt; Latency: 0, Cache Line Size: 32 bytes&lt;BR /&gt; Interrupt: pin A routed to IRQ 29&lt;BR /&gt; Bus: primary=00, secondary=01, subordinate=01, sec-latency=0&lt;BR /&gt; I/O behind bridge: 0000f000-00000fff&lt;BR /&gt; Memory behind bridge: fff00000-000fffff&lt;BR /&gt; Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff&lt;BR /&gt; Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast &amp;gt;TAbort- &amp;lt;TAbort- &amp;lt;MAbort+ &amp;lt;SERR- &amp;lt;PERR-&lt;BR /&gt; Expansion ROM at 4040000000 [disabled] [size=2K]&lt;BR /&gt; BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- &amp;gt;Reset- FastB2B-&lt;BR /&gt; PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-&lt;BR /&gt; Capabilities: [40] Power Management version 3&lt;BR /&gt; Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)&lt;BR /&gt; Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-&lt;BR /&gt; Capabilities: [50] MSI: Enable- Count=1/16 Maskable- 64bit+&lt;BR /&gt; Address: 0000000000000000 Data: 0000&lt;BR /&gt; Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00&lt;BR /&gt; DevCap: MaxPayload 256 bytes, PhantFunc 0&lt;BR /&gt; ExtTag- RBE+&lt;BR /&gt; DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+&lt;BR /&gt; RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+&lt;BR /&gt; MaxPayload 128 bytes, MaxReadReq 512 bytes&lt;BR /&gt; DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-&lt;BR /&gt; LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L0s, Exit Latency L0s unlimited, L1 unlimited&lt;BR /&gt; ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+&lt;BR /&gt; LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- CommClk+&lt;BR /&gt; ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-&lt;BR /&gt; LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt+&lt;BR /&gt; RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible-&lt;BR /&gt; RootCap: CRSVisible-&lt;BR /&gt; RootSta: PME ReqID 0000, PMEStatus- PMEPending-&lt;BR /&gt; DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not Supported ARIFwd-&lt;BR /&gt; DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-&lt;BR /&gt; LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-&lt;BR /&gt; Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-&lt;BR /&gt; Compliance De-emphasis: -6dB&lt;BR /&gt; LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-&lt;BR /&gt; EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-&lt;BR /&gt; Capabilities: [100 v2] Advanced Error Reporting&lt;BR /&gt; UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-&lt;BR /&gt; UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-&lt;BR /&gt; UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-&lt;BR /&gt; CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-&lt;BR /&gt; CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+&lt;BR /&gt; AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-&lt;BR /&gt; Capabilities: [148 v1] #19&lt;BR /&gt; Kernel driver in use: pcieport&lt;/P&gt;&lt;P&gt;01:00.0 PCI bridge: Pericom Semiconductor Device 2304 (rev 05) (prog-if 00 [Normal decode])&lt;BR /&gt; Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-&lt;BR /&gt; Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast &amp;gt;TAbort- &amp;lt;TAbort- &amp;lt;MAbort- &amp;gt;SERR- &amp;lt;PERR- INTx-&lt;BR /&gt; Latency: 0, Cache Line Size: 32 bytes&lt;BR /&gt; Bus: primary=01, secondary=02, subordinate=04, sec-latency=0&lt;BR /&gt; I/O behind bridge: 0000f000-00000fff&lt;BR /&gt; Memory behind bridge: fff00000-000fffff&lt;BR /&gt; Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff&lt;BR /&gt; Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast &amp;gt;TAbort- &amp;lt;TAbort- &amp;lt;MAbort- &amp;lt;SERR- &amp;lt;PERR-&lt;BR /&gt; BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- &amp;gt;Reset- FastB2B-&lt;BR /&gt; PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-&lt;BR /&gt; Capabilities: [40] Power Management version 3&lt;BR /&gt; Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+)&lt;BR /&gt; Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-&lt;BR /&gt; Capabilities: [5c] Vital Product Data&lt;BR /&gt;pcilib: sysfs_read_vpd: read failed: Input/output error&lt;BR /&gt; Not readable&lt;BR /&gt; Capabilities: [64] Vendor Specific Information: Len=34 &amp;lt;?&amp;gt;&lt;BR /&gt; Capabilities: [b0] Subsystem: Device 0000:0000&lt;BR /&gt; Capabilities: [c0] Express (v2) Upstream Port, MSI 00&lt;BR /&gt; DevCap: MaxPayload 256 bytes, PhantFunc 0&lt;BR /&gt; ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ SlotPowerLimit 0.000W&lt;BR /&gt; DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-&lt;BR /&gt; RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-&lt;BR /&gt; MaxPayload 128 bytes, MaxReadReq 128 bytes&lt;BR /&gt; DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr+ TransPend-&lt;BR /&gt; LnkCap: Port #0, Speed 5GT/s, Width x2, ASPM not supported, Exit Latency L0s &amp;lt;512ns, L1 &amp;lt;1us&lt;BR /&gt; ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-&lt;BR /&gt; LnkCtl: ASPM Disabled; Disabled- CommClk+&lt;BR /&gt; ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-&lt;BR /&gt; LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-&lt;BR /&gt; DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR+, OBFF Via message&lt;BR /&gt; DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled&lt;BR /&gt; LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-&lt;BR /&gt; Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-&lt;BR /&gt; Compliance De-emphasis: -6dB&lt;BR /&gt; LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-&lt;BR /&gt; EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-&lt;BR /&gt; Capabilities: [100 v1] Advanced Error Reporting&lt;BR /&gt; UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-&lt;BR /&gt; UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-&lt;BR /&gt; UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-&lt;BR /&gt; CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+&lt;BR /&gt; CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+&lt;BR /&gt; AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-&lt;BR /&gt; Capabilities: [140 v1] Virtual Channel&lt;BR /&gt; Caps: LPEVC=0 RefClk=100ns PATEntryBits=4&lt;BR /&gt; Arb: Fixed- WRR32- WRR64- WRR128-&lt;BR /&gt; Ctrl: ArbSelect=Fixed&lt;BR /&gt; Status: InProgress-&lt;BR /&gt; VC0: Caps: PATOffset=04 MaxTimeSlots=64 RejSnoopTrans-&lt;BR /&gt; Arb: Fixed+ WRR32- WRR64- WRR128+ TWRR128- WRR256-&lt;BR /&gt; Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff&lt;BR /&gt; Status: NegoPending- InProgress-&lt;BR /&gt; Port Arbitration Table &amp;lt;?&amp;gt;&lt;BR /&gt; Capabilities: [20c v1] Power Budgeting &amp;lt;?&amp;gt;&lt;BR /&gt; Capabilities: [230 v1] Latency Tolerance Reporting&lt;BR /&gt; Max snoop latency: 0ns&lt;BR /&gt; Max no snoop latency: 0ns&lt;BR /&gt; Kernel driver in use: pcieport&lt;/P&gt;&lt;P&gt;02:01.0 PCI bridge: Pericom Semiconductor Device 2304 (rev 05) (prog-if 00 [Normal decode])&lt;BR /&gt; Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+&lt;BR /&gt; Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast &amp;gt;TAbort- &amp;lt;TAbort- &amp;lt;MAbort- &amp;gt;SERR- &amp;lt;PERR- INTx-&lt;BR /&gt; Latency: 0, Cache Line Size: 32 bytes&lt;BR /&gt; Interrupt: pin ? routed to IRQ 30&lt;BR /&gt; Bus: primary=02, secondary=03, subordinate=03, sec-latency=0&lt;BR /&gt; I/O behind bridge: 0000f000-00000fff&lt;BR /&gt; Memory behind bridge: fff00000-000fffff&lt;BR /&gt; Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff&lt;BR /&gt; Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast &amp;gt;TAbort- &amp;lt;TAbort- &amp;lt;MAbort- &amp;lt;SERR- &amp;lt;PERR-&lt;BR /&gt; BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- &amp;gt;Reset- FastB2B-&lt;BR /&gt; PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-&lt;BR /&gt; Capabilities: [40] Power Management version 3&lt;BR /&gt; Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+)&lt;BR /&gt; Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-&lt;BR /&gt; Capabilities: [4c] MSI: Enable+ Count=1/1 Maskable- 64bit+&lt;BR /&gt; Address: 0000000001572000 Data: 0000&lt;BR /&gt; Capabilities: [64] Vendor Specific Information: Len=34 &amp;lt;?&amp;gt;&lt;BR /&gt; Capabilities: [b0] Subsystem: Device 0000:0000&lt;BR /&gt; Capabilities: [c0] Express (v2) Downstream Port (Slot+), MSI 00&lt;BR /&gt; DevCap: MaxPayload 256 bytes, PhantFunc 0&lt;BR /&gt; ExtTag- RBE+&lt;BR /&gt; DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-&lt;BR /&gt; RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-&lt;BR /&gt; MaxPayload 128 bytes, MaxReadReq 128 bytes&lt;BR /&gt; DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-&lt;BR /&gt; LnkCap: Port #1, Speed 5GT/s, Width x1, ASPM not supported, Exit Latency L0s &amp;lt;512ns, L1 &amp;lt;1us&lt;BR /&gt; ClockPM- Surprise- LLActRep- BwNot+ ASPMOptComp-&lt;BR /&gt; LnkCtl: ASPM Disabled; Disabled- CommClk-&lt;BR /&gt; ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-&lt;BR /&gt; LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-&lt;BR /&gt; SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-&lt;BR /&gt; Slot #0, PowerLimit 0.000W; Interlock- NoCompl-&lt;BR /&gt; SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-&lt;BR /&gt; Control: AttnInd Off, PwrInd Off, Power- Interlock-&lt;BR /&gt; SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-&lt;BR /&gt; Changed: MRL- PresDet- LinkState-&lt;BR /&gt; DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR+, OBFF Via message ARIFwd-&lt;BR /&gt; DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-&lt;BR /&gt; LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -3.5dB&lt;BR /&gt; Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-&lt;BR /&gt; Compliance De-emphasis: -6dB&lt;BR /&gt; LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1-&lt;BR /&gt; EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-&lt;BR /&gt; Capabilities: [100 v1] Advanced Error Reporting&lt;BR /&gt; UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-&lt;BR /&gt; UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-&lt;BR /&gt; UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-&lt;BR /&gt; CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-&lt;BR /&gt; CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+&lt;BR /&gt; AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-&lt;BR /&gt; Capabilities: [140 v1] Virtual Channel&lt;BR /&gt; Caps: LPEVC=0 RefClk=100ns PATEntryBits=4&lt;BR /&gt; Arb: Fixed- WRR32- WRR64- WRR128-&lt;BR /&gt; Ctrl: ArbSelect=Fixed&lt;BR /&gt; Status: InProgress-&lt;BR /&gt; VC0: Caps: PATOffset=04 MaxTimeSlots=64 RejSnoopTrans-&lt;BR /&gt; Arb: Fixed+ WRR32- WRR64- WRR128+ TWRR128- WRR256-&lt;BR /&gt; Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff&lt;BR /&gt; Status: NegoPending+ InProgress-&lt;BR /&gt; Port Arbitration Table &amp;lt;?&amp;gt;&lt;BR /&gt; Capabilities: [20c v1] Power Budgeting &amp;lt;?&amp;gt;&lt;BR /&gt; Capabilities: [220 v1] Access Control Services&lt;BR /&gt; ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl+ DirectTrans+&lt;BR /&gt; ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-&lt;BR /&gt; Kernel driver in use: pcieport&lt;/P&gt;&lt;P&gt;02:02.0 PCI bridge: Pericom Semiconductor Device 2304 (rev 05) (prog-if 00 [Normal decode])&lt;BR /&gt; Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+&lt;BR /&gt; Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast &amp;gt;TAbort- &amp;lt;TAbort- &amp;lt;MAbort- &amp;gt;SERR- &amp;lt;PERR- INTx-&lt;BR /&gt; Latency: 0, Cache Line Size: 32 bytes&lt;BR /&gt; Interrupt: pin ? routed to IRQ 31&lt;BR /&gt; Bus: primary=02, secondary=04, subordinate=04, sec-latency=0&lt;BR /&gt; I/O behind bridge: 0000f000-00000fff&lt;BR /&gt; Memory behind bridge: fff00000-000fffff&lt;BR /&gt; Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff&lt;BR /&gt; Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast &amp;gt;TAbort- &amp;lt;TAbort- &amp;lt;MAbort- &amp;lt;SERR- &amp;lt;PERR-&lt;BR /&gt; BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- &amp;gt;Reset- FastB2B-&lt;BR /&gt; PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-&lt;BR /&gt; Capabilities: [40] Power Management version 3&lt;BR /&gt; Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+)&lt;BR /&gt; Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-&lt;BR /&gt; Capabilities: [4c] MSI: Enable+ Count=1/1 Maskable- 64bit+&lt;BR /&gt; Address: 0000000001572000 Data: 0008&lt;BR /&gt; Capabilities: [64] Vendor Specific Information: Len=34 &amp;lt;?&amp;gt;&lt;BR /&gt; Capabilities: [b0] Subsystem: Device 0000:0000&lt;BR /&gt; Capabilities: [c0] Express (v2) Downstream Port (Slot+), MSI 00&lt;BR /&gt; DevCap: MaxPayload 256 bytes, PhantFunc 0&lt;BR /&gt; ExtTag- RBE+&lt;BR /&gt; DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-&lt;BR /&gt; RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-&lt;BR /&gt; MaxPayload 128 bytes, MaxReadReq 128 bytes&lt;BR /&gt; DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-&lt;BR /&gt; LnkCap: Port #2, Speed 5GT/s, Width x1, ASPM not supported, Exit Latency L0s &amp;lt;512ns, L1 &amp;lt;1us&lt;BR /&gt; ClockPM- Surprise- LLActRep- BwNot+ ASPMOptComp-&lt;BR /&gt; LnkCtl: ASPM Disabled; Disabled- CommClk-&lt;BR /&gt; ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-&lt;BR /&gt; LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-&lt;BR /&gt; SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-&lt;BR /&gt; Slot #0, PowerLimit 0.000W; Interlock- NoCompl-&lt;BR /&gt; SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-&lt;BR /&gt; Control: AttnInd Off, PwrInd Off, Power- Interlock-&lt;BR /&gt; SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-&lt;BR /&gt; Changed: MRL- PresDet- LinkState-&lt;BR /&gt; DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR+, OBFF Via message ARIFwd-&lt;BR /&gt; DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-&lt;BR /&gt; LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -3.5dB&lt;BR /&gt; Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-&lt;BR /&gt; Compliance De-emphasis: -6dB&lt;BR /&gt; LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1-&lt;BR /&gt; EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-&lt;BR /&gt; Capabilities: [100 v1] Advanced Error Reporting&lt;BR /&gt; UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-&lt;BR /&gt; UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-&lt;BR /&gt; UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-&lt;BR /&gt; CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-&lt;BR /&gt; CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+&lt;BR /&gt; AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-&lt;BR /&gt; Capabilities: [140 v1] Virtual Channel&lt;BR /&gt; Caps: LPEVC=0 RefClk=100ns PATEntryBits=4&lt;BR /&gt; Arb: Fixed- WRR32- WRR64- WRR128-&lt;BR /&gt; Ctrl: ArbSelect=Fixed&lt;BR /&gt; Status: InProgress-&lt;BR /&gt; VC0: Caps: PATOffset=04 MaxTimeSlots=64 RejSnoopTrans-&lt;BR /&gt; Arb: Fixed+ WRR32- WRR64- WRR128+ TWRR128- WRR256-&lt;BR /&gt; Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff&lt;BR /&gt; Status: NegoPending+ InProgress-&lt;BR /&gt; Port Arbitration Table &amp;lt;?&amp;gt;&lt;BR /&gt; Capabilities: [20c v1] Power Budgeting &amp;lt;?&amp;gt;&lt;BR /&gt; Capabilities: [220 v1] Access Control Services&lt;BR /&gt; ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd+ EgressCtrl+ DirectTrans+&lt;BR /&gt; ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans-&lt;BR /&gt; Kernel driver in use: pcieport&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 20 Jul 2018 06:21:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/PCI-E-Switch-not-normal-working-on-LS1012A/m-p/834752#M3763</guid>
      <dc:creator>jasonwu0527</dc:creator>
      <dc:date>2018-07-20T06:21:26Z</dc:date>
    </item>
    <item>
      <title>Re: PCI-E Switch not normal working on LS1012A</title>
      <link>https://community.nxp.com/t5/Layerscape/PCI-E-Switch-not-normal-working-on-LS1012A/m-p/834753#M3764</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;The issue could be caused by the PCIe link integrity.&lt;/P&gt;&lt;P&gt;How exactly the switch is physically connected to the development board?&lt;/P&gt;&lt;P&gt;Have you checked eye diagrams at receivers?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please consider that it will be more convenient to investigate the issue as a Technical Case:&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/381898"&gt;https://community.nxp.com/thread/381898&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 22 Jul 2018 05:00:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/PCI-E-Switch-not-normal-working-on-LS1012A/m-p/834753#M3764</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2018-07-22T05:00:07Z</dc:date>
    </item>
    <item>
      <title>Re: PCI-E Switch not normal working on LS1012A</title>
      <link>https://community.nxp.com/t5/Layerscape/PCI-E-Switch-not-normal-working-on-LS1012A/m-p/834754#M3765</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #2e3033; background-color: #eef0f2; font-weight: normal; font-size: 12px;"&gt;Have you solved your problem?&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 19 Mar 2019 03:20:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/PCI-E-Switch-not-normal-working-on-LS1012A/m-p/834754#M3765</guid>
      <dc:creator>zhangxiang1</dc:creator>
      <dc:date>2019-03-19T03:20:24Z</dc:date>
    </item>
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