LayerscapeのトピックRe: LS1088 Single source clocking and DDRCLK https://community.nxp.com/t5/Layerscape/LS1088-Single-source-clocking-and-DDRCLK/m-p/830425#M3746 <HTML><HEAD></HEAD><BODY><P>I believe that the Checklist recommendation is connected with the fact that hard-coded RCWs select DDRCLK as DDR PLL source clock. Initial board bring-up could be more complicated if DDRCLK is not applied.</P></BODY></HTML> Fri, 20 Jul 2018 06:02:52 GMT ufedor 2018-07-20T06:02:52Z LS1088 Single source clocking and DDRCLK https://community.nxp.com/t5/Layerscape/LS1088-Single-source-clocking-and-DDRCLK/m-p/830424#M3745 <HTML><HEAD></HEAD><BODY><P>For the LS1088, as with other LS10xx SoC's, I understand DIFF_SYSCLK can be used as a replacement for the single-source SYSCLK and DDRCLK, as well as (1088 only), for SerDes PLL.</P><P></P><P>However, AN5144 (LS1088 design checklist) notes that DDRCLK 'This pin must always be connected to a 66.7-133.3 MHz input clock.'.</P><P><BR />Is this a typo?</P><P>Can I use DIFF_SYSCLK only and pull down DDRCLK to GND, as I can with SYSCLK?</P></BODY></HTML> Thu, 19 Jul 2018 06:36:11 GMT https://community.nxp.com/t5/Layerscape/LS1088-Single-source-clocking-and-DDRCLK/m-p/830424#M3745 mcbridematt 2018-07-19T06:36:11Z Re: LS1088 Single source clocking and DDRCLK https://community.nxp.com/t5/Layerscape/LS1088-Single-source-clocking-and-DDRCLK/m-p/830425#M3746 <HTML><HEAD></HEAD><BODY><P>I believe that the Checklist recommendation is connected with the fact that hard-coded RCWs select DDRCLK as DDR PLL source clock. Initial board bring-up could be more complicated if DDRCLK is not applied.</P></BODY></HTML> Fri, 20 Jul 2018 06:02:52 GMT https://community.nxp.com/t5/Layerscape/LS1088-Single-source-clocking-and-DDRCLK/m-p/830425#M3746 ufedor 2018-07-20T06:02:52Z