LayerscapeのトピックConfiguring SERDES1 for SGMII on LS1046

Configuring SERDES1 for SGMII on LS1046

kzambrano — Thu, 19 Jul 2018 14:08:35 GMT

Hi,

I am evaluating the LS1046ARDB capabilities, and per the documentation I can configure the RCW with 0x3333 to have SGMII on MAC 9 and 10.

I have used Code Warrior to import the PBL, file produced by the LEDE distribution, and modified it using a QorIQ Project with Processor Expert. When burned into the alternate bank, UBOOT resets and comes up on the default bank. I believe this is due to a reset from the PLL failing to lock (per spec).

Is this configuration possible, and if so, what is the recipe? I have tried various combinations of REF_CLK_SEL, which either resets or comes up w/o any working MAC or non-working DTSEC9 and DTSEC10.

Has anyone tried to use a different protocol besides the default 0x1133?

Thanks

Re: Configuring SERDES1 for SGMII on LS1046

ufedor — Fri, 20 Jul 2018 06:49:07 GMT

It is possible that modified RCW is incorrect.

Please consider creating a Technical Case to investigate the issue in detail:

https://community.nxp.com/thread/381898

Re: Configuring SERDES1 for SGMII on LS1046

kzambrano — Tue, 24 Jul 2018 15:15:58 GMT

Thank you,

Did that and found out that the ls1024ardb does not support any other protocol except 0x1333 (2xRGMII, 2xXGFI...). The retimer in front of the SFP+ prevents anything but 10G. Not sure about the PHY connected XFI port, it should be capable of using SGMII, but I have not been successful in getting any output with UBOOT. The goal is to obtain 1G SGMII, but I see that the diagram for the reference board has labeled XFI/2.5G SGMII. Didn't get the memo for that either, is there a limitation there also?

Re: Configuring SERDES1 for SGMII on LS1046

ufedor — Wed, 25 Jul 2018 06:05:29 GMT

> found out that the ls1024ardb

Excuse me, which exactly board is in question?

Re: Configuring SERDES1 for SGMII on LS1046

kzambrano — Wed, 22 Aug 2018 13:01:03 GMT

Sorry ls1046ardb, the only working RCW is 0x1133. I did manage to get a 0x3333 to work on the board, which did allow 1G optical operation from the SFP.