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    <title>LayerscapeのトピックRe: How do I configure DDR_SDRAM_CFG and _2?</title>
    <link>https://community.nxp.com/t5/Layerscape/How-do-I-configure-DDR-SDRAM-CFG-and-2/m-p/802205#M3566</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello &lt;A _jive_internal="true" data-content-finding="Community" data-userid="286500" data-username="tracysmith" href="https://community.nxp.com/people/tracysmith"&gt;Tracy Smith&lt;/A&gt;,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In your u-boot source code, if you use raw timing or reading from SPD method to configure DDR controller, you could define the following in u-boot header file include/configs/&amp;lt;target&amp;gt;.h&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;#define CONFIG_DDR_ECC&lt;BR /&gt;#ifdef CONFIG_DDR_ECC&lt;BR /&gt;#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER&lt;BR /&gt;#define CONFIG_MEM_INIT_VALUE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0xdeadbeef&lt;BR /&gt;#endif&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;TIC&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 11 Sep 2018 06:24:41 GMT</pubDate>
    <dc:creator>yipingwang</dc:creator>
    <dc:date>2018-09-11T06:24:41Z</dc:date>
    <item>
      <title>How do I configure DDR_SDRAM_CFG and _2?</title>
      <link>https://community.nxp.com/t5/Layerscape/How-do-I-configure-DDR-SDRAM-CFG-and-2/m-p/802204#M3565</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Do you have example code on how to configure DDR_SDRAM_CFG_2&lt;SPAN class=""&gt;[D_INIT]&lt;/SPAN&gt;=0b'1 and how to configure DDR_SDRAM_CFG&lt;SPAN class=""&gt;[ECC_EN]&lt;/SPAN&gt;=0b'1?&amp;nbsp; Any recommended uboot code or unit test code available on configuring the DDR registers that you would recommend? Need inbyte/outbyte code to configure registers or whatever you recommend from linux or uboot. Any assistance will be greatly appreciated.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 07 Sep 2018 22:12:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/How-do-I-configure-DDR-SDRAM-CFG-and-2/m-p/802204#M3565</guid>
      <dc:creator>tracysmith</dc:creator>
      <dc:date>2018-09-07T22:12:54Z</dc:date>
    </item>
    <item>
      <title>Re: How do I configure DDR_SDRAM_CFG and _2?</title>
      <link>https://community.nxp.com/t5/Layerscape/How-do-I-configure-DDR-SDRAM-CFG-and-2/m-p/802205#M3566</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello &lt;A _jive_internal="true" data-content-finding="Community" data-userid="286500" data-username="tracysmith" href="https://community.nxp.com/people/tracysmith"&gt;Tracy Smith&lt;/A&gt;,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;In your u-boot source code, if you use raw timing or reading from SPD method to configure DDR controller, you could define the following in u-boot header file include/configs/&amp;lt;target&amp;gt;.h&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;#define CONFIG_DDR_ECC&lt;BR /&gt;#ifdef CONFIG_DDR_ECC&lt;BR /&gt;#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER&lt;BR /&gt;#define CONFIG_MEM_INIT_VALUE&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0xdeadbeef&lt;BR /&gt;#endif&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;TIC&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 11 Sep 2018 06:24:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/How-do-I-configure-DDR-SDRAM-CFG-and-2/m-p/802205#M3566</guid>
      <dc:creator>yipingwang</dc:creator>
      <dc:date>2018-09-11T06:24:41Z</dc:date>
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