topic Re: LS1046ARDB - How to use CMIS-DAP interface for debug ? in Layerscape

LS1046ARDB - How to use CMIS-DAP interface for debug ?

pierre_lp — Mon, 26 Nov 2018 16:07:55 GMT

Hi,

In LS1046ARDB reference manual it is stated that CMIS DAP interface can be used for debugging or flashing applications.

"CMSIS-DAP features a mass storage device (MSD) boot loader, which provides a quick and easy mechanism for loading different CMSIS-DAP applications, such as flash programmers, run control debug interfaces, serial-to-USB converters, and so on."

Figure 2-15 shows that K22 MCU is used to acces JTAG signals, so that it is possible to debug or flash.

How can we use this feature ? Where can we get binairies for K22 MCU ?

Regards.

Re: LS1046ARDB - How to use CMIS-DAP interface for debug ?

Pavel — Tue, 27 Nov 2018 10:18:01 GMT

NXP offers CodeWarrior CW4NET 1801:

https://www.nxp.com/products/processors-and-microcontrollers/additional-processors-and-mcus/codewarrior-development-suites-for-networked-applications:CW-DS-NETAPPS

This CodeWarrior supports CMSIS-DAP for code loading and debugging.

Download and install the latest CMSIS-DAP serial driver for Windows:

https://os.mbed.com/handbook/Windows-serial-configuration#1-download-the-mbed-windows-serial-port

Look at the Section 5.4 of the ARMv8_Targeting_Manual.pdf file about using CMSI-DAP.

This file is available in CodeWarrior folder.

Evaluation version of CodeWarrior provides full functionality during one month.

Have a great day,
Pavel Chubakov

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Re: LS1046ARDB - How to use CMIS-DAP interface for debug ?

pierre_lp — Tue, 23 Apr 2019 08:08:47 GMT

Hi,

For those interested, here is a config file for Open OCD.

# Include script to setup CMSIS debug interface
source [find interface/cmsis-dap.cfg]

# Select transport type
transport select jtag

# Target definition
if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
} else {
    set _CHIPNAME ls1046a
}

if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
} else {
    set _CPUTAPID 0x5ba00477
}

adapter_khz 6000
reset_config srst_only

jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
jtag newtap $_CHIPNAME sap -irlen 8 -expected-id 0x06b3001d

#
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu

target create $_CHIPNAME.sap ls1_sap \
                         -chain-position $_CHIPNAME.sap

## declare the 4 cores
set _TARGETNAME $_CHIPNAME.cpu
set $_TARGETNAME.cti(0) 0x80420000
set $_TARGETNAME.cti(1) 0x80520000
set $_TARGETNAME.cti(2) 0x80620000
set $_TARGETNAME.cti(3) 0x80720000
set $_TARGETNAME.dbgbase(0) 0x80410000
set $_TARGETNAME.dbgbase(1) 0x80510000
set $_TARGETNAME.dbgbase(2) 0x80610000
set $_TARGETNAME.dbgbase(3) 0x80710000

set _smp_command ""

set _cores 4
for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
    cti create cti$_core \
    -dap $_CHIPNAME.dap\
    -ctibase [set $_TARGETNAME.cti($_core)] \
     -ap-num 1
    set _command "target create ${_TARGETNAME}$_core aarch64 \
                         -dap $_CHIPNAME.dap -coreid $_core \
             -dbgbase [set  $_TARGETNAME.dbgbase($_core)]\
             -cti cti$_core"
    if { $_core != 0 } {
        # non-boot core examination may fail
        # set _command "$_command -defer-examine"
        set _smp_command "$_smp_command ${_TARGETNAME}$_core"
    } else {
        set _smp_command "target smp ${_TARGETNAME}$_core"
    }
    eval $_command
}
eval $_smp_command

proc ls1046a_prepare { } {
    # Bypass Trust Zone Controller to allow reading and writing anywhere
    echo "Bypassing TZC..."
    targets ls1046a.sap
    ls1046a.sap mww 0x151021c 0 1
}
$_CHIPNAME.sap configure -event examine-end ls1046a_prepare