<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>Layerscape中的主题 PCIe AC coupling capacitors values</title>
    <link>https://community.nxp.com/t5/Layerscape/PCIe-AC-coupling-capacitors-values/m-p/741140#M3183</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello all,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I have a question on the value of the required AC coupling capacitor for PCIe links.&lt;/P&gt;&lt;P&gt;Indeed, the QorIQ data-sheets (Txxx and LSxxx) specify the AC coupling capacitors depending on the targeted protocol. So, it recommends:&lt;/P&gt;&lt;P&gt;&amp;nbsp;* PCIe GEN2 (2.5 GT/s): CTX =&amp;nbsp;&amp;nbsp; 75 to 200 nF&lt;/P&gt;&lt;P&gt;&amp;nbsp;* PCIe GEN2 (5.0 GT/s): CTX =&amp;nbsp;&amp;nbsp; 75 to 200 nF&lt;/P&gt;&lt;P&gt;&amp;nbsp;* PCIe GEN3 (8.0 GT/s): CTX = 176 to 265 nF&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I observed that the reference boards always have 100 nF capacitor, like on traditional GEN2 designs.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;=&amp;gt; Does GEN3 is implemented on demo-boards ?&lt;/P&gt;&lt;P&gt;=&amp;gt; Should I use capacitor in the range 176-200 nF if I design an interface which can run wether at GEN2 or GEN3 rates ?&lt;/P&gt;&lt;P&gt;=&amp;gt; Or, should I use a classic 220nF capacitor for a PCIe GEN3 capable interface, considering it will be able to negotiate the link down to GEN2 speed ? Will it provide a reliable GEN 2 link ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 02 Nov 2017 09:12:42 GMT</pubDate>
    <dc:creator>xabiven</dc:creator>
    <dc:date>2017-11-02T09:12:42Z</dc:date>
    <item>
      <title>PCIe AC coupling capacitors values</title>
      <link>https://community.nxp.com/t5/Layerscape/PCIe-AC-coupling-capacitors-values/m-p/741140#M3183</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello all,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I have a question on the value of the required AC coupling capacitor for PCIe links.&lt;/P&gt;&lt;P&gt;Indeed, the QorIQ data-sheets (Txxx and LSxxx) specify the AC coupling capacitors depending on the targeted protocol. So, it recommends:&lt;/P&gt;&lt;P&gt;&amp;nbsp;* PCIe GEN2 (2.5 GT/s): CTX =&amp;nbsp;&amp;nbsp; 75 to 200 nF&lt;/P&gt;&lt;P&gt;&amp;nbsp;* PCIe GEN2 (5.0 GT/s): CTX =&amp;nbsp;&amp;nbsp; 75 to 200 nF&lt;/P&gt;&lt;P&gt;&amp;nbsp;* PCIe GEN3 (8.0 GT/s): CTX = 176 to 265 nF&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I observed that the reference boards always have 100 nF capacitor, like on traditional GEN2 designs.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;=&amp;gt; Does GEN3 is implemented on demo-boards ?&lt;/P&gt;&lt;P&gt;=&amp;gt; Should I use capacitor in the range 176-200 nF if I design an interface which can run wether at GEN2 or GEN3 rates ?&lt;/P&gt;&lt;P&gt;=&amp;gt; Or, should I use a classic 220nF capacitor for a PCIe GEN3 capable interface, considering it will be able to negotiate the link down to GEN2 speed ? Will it provide a reliable GEN 2 link ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 02 Nov 2017 09:12:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/PCIe-AC-coupling-capacitors-values/m-p/741140#M3183</guid>
      <dc:creator>xabiven</dc:creator>
      <dc:date>2017-11-02T09:12:42Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe AC coupling capacitors values</title>
      <link>https://community.nxp.com/t5/Layerscape/PCIe-AC-coupling-capacitors-values/m-p/741141#M3184</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;New designs have to have 220 nF AC coupling capacitors which are fine for PCIe Gen 3 as well as Gen 2/Gen 1.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 03 Nov 2017 03:28:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/PCIe-AC-coupling-capacitors-values/m-p/741141#M3184</guid>
      <dc:creator>ufedor</dc:creator>
      <dc:date>2017-11-03T03:28:56Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe AC coupling capacitors values</title>
      <link>https://community.nxp.com/t5/Layerscape/PCIe-AC-coupling-capacitors-values/m-p/741142#M3185</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Ufedor,&lt;/P&gt;&lt;P&gt;It's noted, thanks a lot for you quick feedback&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 06 Nov 2017 08:15:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Layerscape/PCIe-AC-coupling-capacitors-values/m-p/741142#M3185</guid>
      <dc:creator>xabiven</dc:creator>
      <dc:date>2017-11-06T08:15:05Z</dc:date>
    </item>
  </channel>
</rss>

