topic Re: DDR4 clock (MCK) termination in Layerscape https://community.nxp.com/t5/Layerscape/DDR4-clock-MCK-termination/m-p/737145#M3152 <HTML><HEAD></HEAD><BODY><P>The termination circuit was simulated and optimized for the specific layout using HyperLynx.</P><P>Similar method is recommended for new designs.</P></BODY></HTML> Mon, 12 Feb 2018 12:50:39 GMT ufedor 2018-02-12T12:50:39Z DDR4 clock (MCK) termination https://community.nxp.com/t5/Layerscape/DDR4-clock-MCK-termination/m-p/737144#M3151 <HTML><HEAD></HEAD><BODY><P>Hi NXP, in the reference design LS1043ARDB-PA/PB the termination resistor (R470 and R468) is 36 ohm for the differential clock.</P><P>The termination resistor for the single ended signals of the address bus/control&nbsp; (R186+..) is 39 ohm.</P><P></P><P>Why do you use a lower resistance value for the differential signal.than for the adress bus/ control bus?</P><P></P><P>regards Trond Inge Wang</P></BODY></HTML> Mon, 12 Feb 2018 11:30:10 GMT https://community.nxp.com/t5/Layerscape/DDR4-clock-MCK-termination/m-p/737144#M3151 trondwang 2018-02-12T11:30:10Z Re: DDR4 clock (MCK) termination https://community.nxp.com/t5/Layerscape/DDR4-clock-MCK-termination/m-p/737145#M3152 <HTML><HEAD></HEAD><BODY><P>The termination circuit was simulated and optimized for the specific layout using HyperLynx.</P><P>Similar method is recommended for new designs.</P></BODY></HTML> Mon, 12 Feb 2018 12:50:39 GMT https://community.nxp.com/t5/Layerscape/DDR4-clock-MCK-termination/m-p/737145#M3152 ufedor 2018-02-12T12:50:39Z